公开(公告)号：US10833678B1

公开(公告)日：2020-11-10

申请号：US16525913

申请日：2019-07-30

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Paul Armstrong

IPC: H03K19/0948 ,  H03K19/17784

Abstract: In a first example a voltage level-shifting device includes a level-shifting stage circuit. The level-shifting stage circuit includes a first level-shifting inverter circuit to invert a buffered input signal to drive a first internal node, a second level-shifting inverter circuit to invert a buffered inverted input signal to drive a second internal node, a first pre-drive circuit that receives the buffered inverted input signal, and drives the second internal node based on the state of the buffered inverted input signal, and a second pre-drive circuit that receives the buffered input signal, and drives the first internal node based on the state of the buffered input signal.

公开(公告)号：US20210049122A1

公开(公告)日：2021-02-18

申请号：US16540175

申请日：2019-08-14

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Paul Armstrong ,  Scott Beeker ,  Jacquelyn M. Ingemi ,  David P. Hannum

IPC: G06F13/40 ,  H03K19/177

Abstract: An ASIC is disclosed that is formed on a die with multiple functional blocks distributed on the die, each functional block being able to send and to receive data, and each having two inputs labeled slow and fast. The slow input may have a delay component that creates a delay in receiving a data signal, and the fast input may have less delay than the slow input. A switch may be used to couple the slow input and the fast input of a receiving functional block to a data signal based on a distance of the receiving functional block from a sending functional block. The delay in the slow input is used to adjust input data timing to meet setup and hold timing specifications of the functional blocks without altering the ASIC circuit components aside from the functional blocks.