公开(公告)号：US09972387B2

公开(公告)日：2018-05-15

申请号：US15325040

申请日：2014-10-31

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Martin Foltin ,  Yoocharn Jeon ,  Brent Buchanan ,  Erik Ordentlich ,  Naveen Muralimanohar ,  James S. Ignowski ,  Jacquelyn M. Ingemi

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C13/004 ,  G11C7/06 ,  G11C13/0038 ,  G11C13/0059 ,  G11C13/0061 ,  G11C13/0069 ,  G11C13/0097 ,  G11C27/024 ,  G11C2013/0045 ,  G11C2013/0054 ,  G11C2207/068

Abstract: This disclosure provides a circuit that includes a ramp generator to apply a voltage ramp to a resistive memory cell. A sensing circuit can enable the ramp generator and monitor a current output received from the resistive memory cell in response to the applied voltage ramp, wherein the sensing circuit compares the current output to a predetermined current threshold to determine the state of the resistive memory cell.

公开(公告)号：US20210049122A1

公开(公告)日：2021-02-18

申请号：US16540175

申请日：2019-08-14

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Paul Armstrong ,  Scott Beeker ,  Jacquelyn M. Ingemi ,  David P. Hannum

IPC: G06F13/40 ,  H03K19/177

Abstract: An ASIC is disclosed that is formed on a die with multiple functional blocks distributed on the die, each functional block being able to send and to receive data, and each having two inputs labeled slow and fast. The slow input may have a delay component that creates a delay in receiving a data signal, and the fast input may have less delay than the slow input. A switch may be used to couple the slow input and the fast input of a receiving functional block to a data signal based on a distance of the receiving functional block from a sending functional block. The delay in the slow input is used to adjust input data timing to meet setup and hold timing specifications of the functional blocks without altering the ASIC circuit components aside from the functional blocks.

公开(公告)号：US20170206956A1

公开(公告)日：2017-07-20

申请号：US15325040

申请日：2014-10-31

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Martin Foltin ,  Yoocharn Jeon ,  Brent Buchanan ,  Erik Ordentlich ,  Naveen Muralimanohar ,  James S. Ignowski ,  Jacquelyn M. Ingemi

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C7/06 ,  G11C13/0038 ,  G11C13/0059 ,  G11C13/0061 ,  G11C13/0069 ,  G11C13/0097 ,  G11C27/024 ,  G11C2013/0045 ,  G11C2013/0054 ,  G11C2207/068

Abstract: This disclosure provides a circuit that includes a ramp generator to apply a voltage ramp to a resistive memory cell. A sensing circuit can enable the ramp generator and monitor a current output received from the resistive memory cell in response to the applied voltage ramp, wherein the sensing circuit compares the current output to a predetermined current threshold to determine the state of the resistive memory cell.