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公开(公告)号：US20230074935A1
公开(公告)日：2023-03-09
申请号：US17664477
申请日：2022-05-23
发明人： Yinchuan GU
IPC分类号： H03K5/22 , H03K5/135 , H03K5/08 , H03K19/17784
摘要： The present disclosure provides a comparator and a decision feedback equalization circuit. The comparator includes: a first sampling circuit configured to generate, under the control of a first control signal and a clock signal, first differential signals according to a signal to be compared and a first reference signal; a first positive feedback circuit configured to accelerate a difference between the first differential signals; a second sampling circuit configured to generate, under the control of a second control signal and the clock signal, second differential signals according to the signal to be compared and a second reference signal, where the first reference signal is larger than the second reference signal; a second positive feedback circuit configured to accelerate a difference between the second differential signals.
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公开(公告)号：US11585854B1
公开(公告)日：2023-02-21
申请号：US16108596
申请日：2018-08-22
申请人： Xilinx, Inc.
发明人： Da Cheng , Nui Chong , Amitava Majumdar , Ping-Chin Yeh , Cheang-Whang Chang
IPC分类号： G01R31/319 , G01R31/3185 , G01R31/317 , G01R31/28 , H03K3/03 , G06F13/42 , H03L7/099 , H03K19/00 , G06F1/324 , G06F1/3206 , H03K19/17784 , G01R19/165 , G06F1/26 , G06F1/32 , G06F1/3203 , G06F1/3296
摘要： Circuits and methods involve an integrated circuit (IC) device, a plurality of application-specific sub-circuits, and a plurality of instances of a measuring circuit. The application-specific sub-circuits are disposed within respective areas of the IC device. Each instance of the measuring circuit is associated with one of the application-specific sub-circuits and is disposed within a respective one of the areas of the device. Each instance of the measuring circuit further includes a ring oscillator and a register for storage of a value indicative of an interval of time. Each instance of the measuring circuit is configured to measure passage of the interval of time based on a first clock signal, count oscillations of an output signal of the ring oscillator during the interval of time, and output a value indicating a number of oscillations counted during the interval of time.
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公开(公告)号：US20230026294A1
公开(公告)日：2023-01-26
申请号：US17652905
申请日：2022-02-28
IPC分类号： H03K19/1776 , G11C11/16 , G11C13/00 , H03K19/17724 , H03K19/17784
摘要： The present disclosure is drawn to, among other things, a configuration bit including at least four resistive elements and a voltage amplifier. At least two first resistive elements may be electrically connected in series via a first electrode and at least two second resistive elements may be electrically connected in series via a second electrode. The at least two first resistive elements may be electrically connected in parallel to the at least two second resistive elements via a third electrode and a fourth electrode. The first electrode and the second electrode may be electrically connected to a voltage supply. The third electrode and the fourth electrode may be electrically connected to an input of the voltage amplifier.
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公开(公告)号：US11469761B1
公开(公告)日：2022-10-11
申请号：US17472066
申请日：2021-09-10
IPC分类号： H03K19/018 , H03K19/0185 , H03K19/17784 , H03K5/24 , H03K5/05 , H03K5/00
摘要： Systems and methods for frequency reference generation are described. In an embodiment, a frequency reference circuit, includes: a bandgap proportional to temperature (PTAT) generator circuit that generates a bandgap PTAT current; a resistor complementary to temperature (CTAT) generator circuit that generates a resistor CTAT current; an adder that adds the PTAT current and the CTAT current to generate a constant current Icons; a switched-resistor (switched-R) circuit that receives the constant current Icons and a previously generated output clock and generates an output; a bandgap voltage reference generator circuit that generates a bandgap voltage VBG; an integrator circuit that receives the output of the switched-R circuit and the bandgap voltage VBG and generates an output; and a voltage-controlled oscillator (VCO) circuit that receives the output of the integrator circuit and generates a frequency reference.
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公开(公告)号：US20220321127A1
公开(公告)日：2022-10-06
申请号：US17468853
申请日：2021-09-08
发明人： Jae-Mun OH , Byung-Do YANG , Jung-Ho KIM
IPC分类号： H03K19/1776 , H03K19/17784
摘要： Disclosed herein is a memory-type camouflaged logic gate using transistors having different threshold voltages. The camouflaged logic gate may include two or more candidate logic gates, memory, the output signal of which is adjusted based on two or more transistors having different threshold voltages, and a multiplexer for selectively outputting the output of one of the two or more candidate logic gates depending on the output signal of the memory.
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公开(公告)号：US20220223186A1
公开(公告)日：2022-07-14
申请号：US17669565
申请日：2022-02-11
发明人： Kangling Ji
IPC分类号： G11C7/10 , H03K19/0175 , H03K19/17784 , H03K19/20
摘要： Embodiments of the disclosure provide a comparison system including at least one comparison circuit, the comparison circuit including: a common circuit, connected to a power supply signal and a ground signal, and configured to control output of the power supply signal or the ground signal based on a first signal and a second signal which are inverted; a first logical circuit, connected to the common circuit, and configured to receive a third signal and a fourth signal which are inverted, and output a first operation signal which is an exclusive OR (XOR) of the first signal and the third signal; and a second logical circuit, connected to the common circuit, and configured to receive the third signal and the fourth signal, and output a second operation signal which is a not exclusive OR (XNOR) of the first signal and the third signal.
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公开(公告)号：US20220116045A1
公开(公告)日：2022-04-14
申请号：US17559569
申请日：2021-12-22
申请人： Intel Corporation
发明人： Mahesh K. Kumashikar , Ankireddy Nalamalpu , MD Altaf Hossain , Atul Maheshwari , Yuet Li , Mahesh A. Iyer
IPC分类号： H03K19/17736 , H03K19/1776 , H03K19/17784
摘要： An integrated circuit device that includes programmable logic circuitry that includes a plurality of regions each configured to operate at different voltage levels. The regions may be separated by level shifters that enable communication between the different voltage level regions. The integrated circuitry may also include software that performs voltage aware placement and routing for a user register-transfer level design, and may direct logic to regions according to voltages defined for the regions.
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公开(公告)号：US20220085810A1
公开(公告)日：2022-03-17
申请号：US17419046
申请日：2019-12-26
申请人： SOFICS BVBA
IPC分类号： H03K19/0185 , H03K19/00 , H03K19/17784 , H03K19/17736 , H03K19/12
摘要： A driver for a shared bus, such as a LIN bus, having a supply node (Vbat), a bus node (LIN), a transmit data input node (TX) and a receive data output node (RX), said driver comprising: a pull-up circuitry between the supply node and the bus node, driver circuitry (100) having a control input connected to the transmit data input node, feedback circuitry (200) configured to provide feedback from the shared bus to the control input of the driver circuitry; said feedback circuitry comprising copy circuitry (210) configured to obtain at least one copy signal representative for a signal on the bus node, filter circuitry (220) configured to low-pass filter the at least one copy signal, derivative circuitry (230) configured to obtain at least one derivative signal representative for the speed at which the signal on the bus node varies.
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公开(公告)号：US11228313B2
公开(公告)日：2022-01-18
申请号：US16878952
申请日：2020-05-20
发明人： Wen-Yi Mao , Li-Li Tan
IPC分类号： H03K19/0175 , H03K19/173 , G06F13/40 , G06F13/42 , H03K19/0185 , H03K19/17784 , H03K19/017
摘要： A signal transmission circuit is provided. A tri-state logic circuit includes an enabling terminal, an input terminal and an output terminal, and is conducted and unconducted when the enabling terminal is at a high and a low state respectively. A pull-up circuit pulls up a voltage level of the output terminal. A first and a second multiplexers respectively output an enabling signal and an output signal to the enabling terminal and the input terminal according to a first status of a selection signal and respectively output a high state signal according to a second status of the selection signal. A selection circuit generates the selection signal having the first status when the voltage level is not larger than a first threshold value, having the second status after the voltage level is larger than the first threshold value and having the first status afterwards.
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公开(公告)号：US10777257B1
公开(公告)日：2020-09-15
申请号：US16707783
申请日：2019-12-09
发明人： Tetsuya Arai , Junki Taniguchi
IPC分类号： G11C11/40 , H03K19/177 , G11C11/4093 , G11C11/4096 , H03K19/00 , H03K3/037 , H03K19/094 , H03K19/17772 , H03H11/28 , H03K19/17784
摘要： Disclosed herein is an apparatus that includes: a data terminal; a first output transistor connected between the data terminal and a first power line supplying a first power potential; a first tristate circuit including an output node connected to a control electrode of the first output transistor, a first pull-up transistor configured to drive the output node to a first logic level, and a first pull-down transistor configured to drive the output node to a second logic level; and a second tristate circuit including an output node connected to the control electrode of the first output transistor, a second pull-up transistor configured to drive the output node to the first logic level, and a second pull-down transistor configured to drive the output node to the second logic level. The second pull-up and pull-down transistors have a different threshold voltage from the first pull-up and pull-down transistors.
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