公开(公告)号：US11334132B2

公开(公告)日：2022-05-17

申请号：US16481871

申请日：2018-04-18

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Binh T Truong ,  Mengistu Taye ,  Javier Enrique Guerrero

IPC: G06F1/26 ,  G06F13/42

Abstract: The examples include methods and apparatuses to power a peripheral device through a PUSB port. Powering a peripheral device through a PUSB port includes receiving a request for a plurality of PUSB power options for a PUSB port coupled to a device, providing the plurality of PUSB power options in a hardware initialization system, receiving a selection PUSB power option from the plurality of PUSB power options, and providing a power, corresponding to the selection PUSB power option, to the PUSB port.

公开(公告)号：US20210333854A1

公开(公告)日：2021-10-28

申请号：US16481871

申请日：2018-04-18

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Binh T Truong ,  Mengistu Taye ,  Javier Enrique Guerrero

IPC: G06F1/26 ,  G06F13/42

Abstract: The examples include methods and apparatuses to power a peripheral device through a PUSB port. Powering a peripheral device through a PUSB port includes receiving a request for a plurality of PUSB power options for a PUSB port coupled to a device, providing the plurality of PUSB power options in a hardware initialization system, receiving a selection PUSB power option from the plurality of PUSB power options, and providing a power, corresponding to the selection PUSB power option, to the PUSB port.

公开(公告)号：US11379399B2

公开(公告)日：2022-07-05

申请号：US17043793

申请日：2018-06-05

Applicant: Hewlett-Packard Development Company, L.P.

Inventor： Mengistu Taye ,  Evan Lu

IPC: G06F13/40 ,  G06F13/38 ,  G06F13/42

Abstract: Example implementations relate to route demultiplexed signal pairs. In some examples, a motherboard of a computing device can include a chipset, a first Peripheral Component Interconnect Express (PCIe) bus, a second PCIe bus, a riser slot, and a demultiplexer connected to the chipset to selectively route particular signal pairs from the chipset to at least one of the first PCIe bus, the second PCIe bus, and the riser slot based on whether a riser card is connected to the riser slot.