公开(公告)号：US20140173170A1

公开(公告)日：2014-06-19

申请号：US13715163

申请日：2012-12-14

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Naveen Muralimanohar ,  Norman P. Jouppi ,  Rajeev Balasubramonian ,  Seth Pugsley ,  Niladrish Chatterjee ,  Alan Lynn Davis

IPC: G06F12/02

CPC classification number: G06F13/1678 ,  G06F13/16 ,  Y02D10/14

Abstract: A multiple subarray-access memory system is disclosed. The system includes a plurality of memory chips, each including a plurality of subarrays and a memory controller in communication. with the memory chips, the memory controller to receive a memory fetch width (“MFW”) instruction during an operating system start-up and responsive to the MFW instruction to fix a quantity of the subarrays that will be activated in response to memory access requests.

Abstract translation: 公开了一种多重子阵列存取存储器系统。 该系统包括多个存储器芯片，每个存储器芯片包括多个子阵列和通信的存储器控​​制器。 利用存储器芯片，存储器控制器在操作系统启动期间接收存储器提取宽度（“MFW”）指令，并且响应于MFW指令来修复将响应于存储器访问请求而被激活的数量的子阵列 。