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公开(公告)号：US09898365B2
公开(公告)日：2018-02-20
申请号：US14899708
申请日：2013-07-31
Applicant: Hewlett-Packard Development Company, L.P.
Inventor： Naveen Muralimanohar , Doe Hyun Yoon
IPC: G06F11/10 , G06F12/08 , G06F3/06 , G06F12/0866
CPC classification number: G06F11/1076 , G06F3/0619 , G06F3/064 , G06F3/0673 , G06F11/1012 , G06F11/108 , G06F12/0866 , G06F2212/1032 , G06F2212/281
Abstract: A method that includes evaluating, with a controller, local error detection (LED) information in response to a first memory access operation is disclosed. The LED information is evaluated per cache line segment of data associated with a rank of a memory. The method further includes determining an error in at least one of the cache line segments based on an error detection code and determining whether global error correction (GEC) data for a first cache line associated with the at least one cache line segment is stored in a GEC cache in the controller. The method also includes correcting the first cache line associated with the at least one cache line segment based on the GEC data retrieved from the GEC cache in the controller without accessing GEC data from a memory.
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公开(公告)号：US09832550B2
公开(公告)日：2017-11-28
申请号：US14764960
申请日：2013-01-31
Applicant: Hewlett-Packard Development Company, L.P.
Inventor： Moray McLaren , Raymond G Beausoleil , Norman Paul Jouppi , Marco Fiorentino , Alan Lynn Davis , Naveen Muralimanohar , Sheng Li
CPC classification number: H04Q11/0005 , H04J14/02 , H04Q11/0003 , H04Q11/0066 , H04Q11/0071 , H04Q2011/0016 , H04Q2011/002 , H04Q2011/0039
Abstract: A system can include an optical multiplexer to combine a plurality of optical input signals having respective wavelengths into a wide-channel optical input signal that is provided to an input channel. The system also includes a photonic packet switch comprising a switch core and a plurality of ports defining a switch radix of the photonic packet switch. The input channel and an output channel can be associated with one of the plurality of ports. The photonic packet switch can process the wide-channel optical input signal and can generate a wide-channel optical output signal that is provided to the output channel. The system further includes an optical demultiplexer to separate the wide-channel optical output signal into a plurality of optical output signals having respective wavelengths. The optical multiplexer and the optical demultiplexer can collectively provide the system with a radix greater than the switch radix.
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公开(公告)号：US20160139988A1
公开(公告)日：2016-05-19
申请号：US14898539
申请日：2013-07-31
Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Inventor： Naveen Muralimanohar , Erik Ordentlich
CPC classification number: G06F11/1076 , G06F3/0619 , G06F3/0644 , G06F3/0683 , G06F11/1004 , G06F11/108 , H03M13/09 , H03M13/096 , H03M13/1515 , H03M13/152 , H03M13/2906
Abstract: Operating a memory unit during a memory access operation. The memory unit includes a configuration of N data chips. A line of data stored in the memory unit is divided, with a controller, into a first portion and a second portion. The first portion of the line of data is encoded, with an outer code encoder, to generate an outer code output. The second portion of the line of data and the outer code output from the outer code encoder are encoded, with an inner code encoder, to generate an inner code output. A first layer of protection for the line of data is generated based on the inner code output and is stored to the memory unit, where the first layer of protection includes local error detection (LED) information combined with the line of data. A second layer of protection for the line of data is generated based on the first layer of protection and is stored to the memory unit. A decoding operation to retrieve the line of data is performing at the controller.
Abstract translation: 在存储器访问操作期间操作存储器单元。 存储单元包括N个数据芯片的配置。 存储在存储器单元中的数据线与控制器分成第一部分和第二部分。 数据行的第一部分使用外部代码编码器进行编码，以生成外部代码输出。 数据行的第二部分和从外码编码器输出的外码用内码编码器编码，以产生内码输出。 基于内部代码输出产生用于数据线的第一层保护，并将其存储到存储单元中，其中第一层保护包括与数据行组合的本地错误检测（LED）信息。 基于第一层保护来生成数据线的第二层保护层，并将其存储到存储器单元中。 在控制器执行用于检索数据行的解码操作。
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4.发明申请LOOKUP OF A DATA STRUCTURE CONTAINING A MAPPING BETWEEN A VIRTUAL ADDRESS SPACE AND A PHYSICAL ADDRESS SPACE 审中-公开查看包含虚拟地址空间和物理地址空间之间的映射的数据结构公开(公告)号：US20160103766A1
公开(公告)日：2016-04-14
申请号：US14786268
申请日：2013-07-01
Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Inventor： Naveen Muralimanohar , Kevin T. Lim , Norman Paul Jouppi , Doe Hyun Yoon
CPC classification number: G06F12/1009 , G06F12/0802 , G06F12/0875 , G06F12/1027 , G06F12/1054 , G06F12/1063 , G06F2212/1021 , G06F2212/452 , G06F2212/50 , G06F2212/68 , G06F2212/681
Abstract: A memory region stores a data structure that contains a mapping between a virtual address space and a physical address space of a memory. A portion of the mapping is cached in a cache memory. In response to a miss in the cache memory responsive to a lookup of a virtual address of a request, an indication is sent to the buffer device. In response to the indication, a hardware controller on the buffer device performs a lookup of the data structure in the memory region to find a physical address corresponding to the virtual address.
Abstract translation: 存储器区域存储包含虚拟地址空间和存储器的物理地址空间之间的映射的数据结构。 映射的一部分被缓存在高速缓冲存储器中。 响应于对请求的虚拟地址的查找而响应于高速缓冲存储器中的未命中，向缓冲器设备发送指示。 响应于该指示，缓冲器装置上的硬件控制器执行对存储器区域中的数据结构的查找以找到与虚拟地址相对应的物理地址。
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5.发明申请公开(公告)号：US20160055095A1
公开(公告)日：2016-02-25
申请号：US14780544
申请日：2013-03-28
Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Inventor： Paolo Faraboschi , Hans Boehm , Dhruva Chakrabarti , Naveen Muralimanohar
CPC classification number: G06F12/0893 , G06F3/061 , G06F3/0638 , G06F3/0679 , G06F12/0804 , G06F2212/1016 , G06F2212/202 , G06F2212/60
Abstract: A method for performing memory operations is provided. One or more processors can determine that at least a portion of data stored in a cache memory of the one or more processors is to be stored in the main memory. One or more ranges of addresses of the main memory is determined that correspond to a plurality of cache lines in the cache memory. A set of cache lines corresponding to addresses in the one or more ranges of addresses is identified, so that data stored in the identified set can be stored in the main memory. For each cache line of the identified set having data that has been modified since that cache line was first loaded to the cache memory or since a previous store operation, data stored in that cache line is caused to be stored in the main memory.
Abstract translation: 提供了一种执行存储器操作的方法。 一个或多个处理器可以确定存储在一个或多个处理器的高速缓冲存储器中的数据的至少一部分将被存储在主存储器中。 确定与主存储器中的多个高速缓存行相对应的主存储器的一个或多个范围的地址。 识别与一个或多个地址范围中的地址对应的一组高速缓存行，使得存储在所识别的集合中的数据可以存储在主存储器中。 对于具有已经被修改的数据的已识别集合的每个高速缓存行，因为该高速缓存行首先被加载到高速缓存存储器中或者由于先前存储操作，存储在该高速缓存行中的数据被存储在主存储器中。
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Patent Agency Ranking
公开(公告)号：US09852792B2
公开(公告)日：2017-12-26
申请号：US14764135
申请日：2013-01-31
Applicant: Hewlett-Packard Development Company, L.P.
Inventor： Naveen Muralimanohar , Han Bin Yoon , Norman Paul Jouppi
CPC classification number: G11C13/0061 , G06F12/0246 , G11C11/5628 , G11C11/5678 , G11C11/5685 , G11C13/0002 , G11C13/0004 , G11C13/004 , G11C13/0069 , G11C16/10 , G11C16/26 , G11C2207/2272 , Y02D10/13
Abstract: A non-volatile multi-level cell (“MLC”) memory device is disclosed. The memory device has an array of non-volatile memory cells, an array of non-volatile memory cells, with each non-volatile memory cell storing multiple groups of bits. A row buffer in the memory device has multiple buffer portions, each buffer portion storing one or more bits from the memory cells and having different read and write latencies and energies.
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公开(公告)号：US09620181B2
公开(公告)日：2017-04-11
申请号：US14764673
申请日：2013-01-31
Applicant: Hewlett-Packard Development Company, L.P.
Inventor： Sheng Li , Norman Paul Jouppi , Naveen Muralimanohar
IPC: G06F12/00 , G11C7/10 , G11C11/408 , G11C11/4093 , G11C15/00 , G06F12/0893 , G06F12/0875
CPC classification number: G11C7/1072 , G06F12/0875 , G06F12/0893 , G06F2212/3042 , G06F2212/452 , G11C7/1084 , G11C11/4087 , G11C11/4093 , G11C15/00 , Y02D10/13
Abstract: According to an example, a method for adaptive-granularity row buffer (AG-RB) caching may include determining whether to cache data to a RB cache, and adjusting, by a processor or a memory side logic, an amount of the data to cache to the RB cache for different memory accesses, such as dynamic random-access memory (DRAM) accesses. According to another example, an AG-RB cache apparatus may include a 3D stacked DRAM including a plurality of DRAM dies including one or more DRAM banks, and a logic die including a RB cache. The AG-RB cache apparatus may further include a processor die including a memory controller including a predictor module to determine whether to cache data to the RB cache, and to adjust an amount of the data to cache to the RB cache for different DRAM accesses.
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公开(公告)号：US20160147598A1
公开(公告)日：2016-05-26
申请号：US14899669
申请日：2013-07-31
Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Inventor： Naveen Muralimanohar , Erik Ordentlich
IPC: G06F11/10
CPC classification number: G06F11/1064 , G06F11/1012 , G06F11/1016
Abstract: A method for operating a memory unit is disclosed. The method includes encoding data from a cache line divided in a plurality of groups and generating a plurality of codewords. The method further includes storing the LED data for the cache line combined with the data of the cache line retrieved from a first portion of the codewords across a plurality of chips in the memory unit to create a first tier of protection. The method also includes storing the GEC data for the cache line retrieved from a second portion of the codewords across the plurality of chips to create a second tier of protection for the cache line. The method also includes receiving information corresponding to the first tier of protection, determining whether an error exists in the data of the cache line, decoding the data of the cache line, and outputting the data of the cache line at the controller.
Abstract translation: 公开了一种用于操作存储器单元的方法。 该方法包括从分组在多个组中的高速缓存行编码数据并生成多个码字。 该方法还包括存储与存储器单元中的多个芯片上的从码字的第一部分检索的高速缓存线的数据结合的高速缓存行的LED数据，以创建第一层保护。 该方法还包括存储从跨越多个码片的码字的第二部分检索的高速缓存线的GEC数据，以创建高速缓存线的第二保护层。 该方法还包括接收对应于第一层保护的信息，确定高速缓存行的数据中是否存在错误，解码高速缓存行的数据，以及在控制器处输出高速缓存行的数据。
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公开(公告)号：US20140173170A1
公开(公告)日：2014-06-19
申请号：US13715163
申请日：2012-12-14
Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
Inventor： Naveen Muralimanohar , Norman P. Jouppi , Rajeev Balasubramonian , Seth Pugsley , Niladrish Chatterjee , Alan Lynn Davis
IPC: G06F12/02
CPC classification number: G06F13/1678 , G06F13/16 , Y02D10/14
Abstract: A multiple subarray-access memory system is disclosed. The system includes a plurality of memory chips, each including a plurality of subarrays and a memory controller in communication. with the memory chips, the memory controller to receive a memory fetch width (“MFW”) instruction during an operating system start-up and responsive to the MFW instruction to fix a quantity of the subarrays that will be activated in response to memory access requests.
Abstract translation: 公开了一种多重子阵列存取存储器系统。 该系统包括多个存储器芯片，每个存储器芯片包括多个子阵列和通信的存储器控制器。 利用存储器芯片，存储器控制器在操作系统启动期间接收存储器提取宽度（“MFW”）指令，并且响应于MFW指令来修复将响应于存储器访问请求而被激活的数量的子阵列 。
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公开(公告)号：US09934085B2
公开(公告)日：2018-04-03
申请号：US14785071
申请日：2013-05-29
Applicant: Hewlett-Packard Development Company, L.P.
Inventor： Doe-Hyun Yoon , Jichuan Chang , Naveen Muralimanohar , Parthasarathy Ranganathan , Robert Schreiber , Norman Paul Jouppi
CPC classification number: G06F11/085 , G06F11/1048 , G06F11/1469 , G06F11/1471 , G06F17/30424
Abstract: A detector detects, using an error code, an error in data stored in a memory. The detector determines whether the error is uncorrectable using the error code. In response to determining that the error is uncorrectable, an error handler associated with an application is invoked to handle the error in the data by recovering the data to an application-wide consistent state.
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