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    MULTIPLE SUBARRAY MEMORY ACCESS
    1.
    发明申请
    MULTIPLE SUBARRAY MEMORY ACCESS 审中-公开
    多个子目录存储器访问

    公开(公告)号：US20140173170A1

    公开(公告)日：2014-06-19

    申请号：US13715163

    申请日：2012-12-14

    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

    Inventor： Naveen Muralimanohar ,  Norman P. Jouppi ,  Rajeev Balasubramonian ,  Seth Pugsley ,  Niladrish Chatterjee ,  Alan Lynn Davis

    IPC: G06F12/02

    CPC classification number: G06F13/1678 ,  G06F13/16 ,  Y02D10/14

    Abstract: A multiple subarray-access memory system is disclosed. The system includes a plurality of memory chips, each including a plurality of subarrays and a memory controller in communication. with the memory chips, the memory controller to receive a memory fetch width (“MFW”) instruction during an operating system start-up and responsive to the MFW instruction to fix a quantity of the subarrays that will be activated in response to memory access requests.

    Abstract translation: 公开了一种多重子阵列存取存储器系统。 该系统包括多个存储器芯片，每个存储器芯片包括多个子阵列和通信的存储器控​​制器。 利用存储器芯片，存储器控制器在操作系统启动期间接收存储器提取宽度（“MFW”）指令，并且响应于MFW指令来修复将响应于存储器访问请求而被激活的数量的子阵列 。

    CACHING DATA IN A MEMORY SYSTEM HAVING MEMORY NODES AT DIFFERENT HIERARCHICAL LEVELS
    4.
    发明申请
    CACHING DATA IN A MEMORY SYSTEM HAVING MEMORY NODES AT DIFFERENT HIERARCHICAL LEVELS 审中-公开
    在具有不同分层级的记忆体的存储系统中缓存数据

    公开(公告)号：US20150378913A1

    公开(公告)日：2015-12-31

    申请号：US14764651

    申请日：2013-03-20

    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

    Inventor： Norman P. Jouppi ,  Sheng Li ,  Ke Chen

    IPC: G06F12/08

    CPC classification number: G06F12/0844 ,  G06F12/08 ,  G06F12/0811 ,  G06F2212/1024 ,  G06F2212/1028 ,  G06F2212/283 ,  G06F2212/304 ,  G06F2212/604

    Abstract: A memory system includes a plurality of memory nodes provided at different hierarchical levels of the memory system, each of the memory nodes including a corresponding memory storage and a cache. A memory node at a first of the different hierarchical levels is coupled to a processor with lower communication latency than a memory node at a second of the different hierarchical levels. The memory nodes are to cooperate to decide which of the memory nodes is to cache data of a given one of the memory nodes.

    Abstract translation: 存储器系统包括在存储器系统的不同层级提供的多个存储器节点，每个存储器节点包括对应的存储器存储器和高速缓存。 处于不同等级级别的第二级的存储器节点被耦合到具有比存储器节点低的通信延迟的处理器。 存储器节点将协作以确定哪个存储器节点将缓存给定的一个存储器节点的数据。

    Efficient and Reliable Memory Systems with Adaptive ECC and Granularity Switching
    8.
    发明申请
    Efficient and Reliable Memory Systems with Adaptive ECC and Granularity Switching 审中-公开
    具有自适应ECC和粒度切换的高效可靠的存储系统

    公开(公告)号：US20150278004A1

    公开(公告)日：2015-10-01

    申请号：US14437684

    申请日：2012-11-02

    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

    Inventor： Sheng Li ,  Norman P. Jouppi ,  Doe Hyun Yoon

    IPC: G06F11/07 ,  G06F12/08

    CPC classification number: G06F11/0787 ,  G06F11/073 ,  G06F11/1048 ,  G06F12/0875 ,  G06F2212/45 ,  G11C7/20 ,  G11C29/028 ,  G11C29/42 ,  G11C29/52 ,  G11C2029/0411

    Abstract: Example methods, systems, and apparatus to provide selective memory error protection and memory access granularity are disclosed herein. An example system includes a memory controller to determine a selected memory mode based on a request. The memory mode indicates that a memory page is to store a corresponding type of error protection information and is to store data for retrieval using a corresponding access granularity. The memory controller is to store the data and the error protection information in the memory page for retrieval using the error protection information and the access granularity.

    Abstract translation: 本文公开了提供选择性存储器错误保护和存储器访问粒度的示例性方法，系统和装置。 示例系统包括存储器控制器，用于基于请求确定选择的存储器模式。 存储器模式指示存储器页面存储相应类型的错误保护信息，并且是使用对应的访问粒度来存储用于检索的数据。 存储器控制器将使用错误保护信息和访问粒度将数据和错误保护信息存储在存储器页面中以进行检索。

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