公开(公告)号：US20220063262A1

公开(公告)日：2022-03-03

申请号：US17454069

申请日：2021-11-09

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Boon Bing Ng ,  Rui Pan ,  Mohan Kumar Sudhakar ,  Brendan Hall

IPC: B41J2/045

Abstract: In some examples, a circuit includes a data line, an input line, a first memory element, and a decoder to receive an address and to enable the first memory element for access in response to the address. The selector is responsive to the data line to select the first memory element, where the selector is to select the first memory element responsive to the data line having a first value, and where the data line is to communicate data of a second memory element in response to the second memory element being enabled for access. The input line is to communicate data of the first memory element in response to the first memory element being selected by the selector.

公开(公告)号：US20210094281A1

公开(公告)日：2021-04-01

申请号：US16608061

申请日：2017-07-06

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Boon Bing NG ,  Rui Pan ,  Mohan Kumar Sudhakar ,  Hang Ru Goy

IPC: B41J2/045

Abstract: In some examples, a circuit for use with a fluid ejection device includes a plurality of decoders responsive to a common address to activate respective control signals at different times for selecting respective memories of the fluid ejection device. Each respective decoder of the plurality of decoders comprising a discharge switch to deactivate a control signal of the respective decoder while another decoder of the plurality of decoders is activating a control signal in response to the common address.

公开(公告)号：US10913265B2

公开(公告)日：2021-02-09

申请号：US16607441

申请日：2017-07-06

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Boon Bing Ng ,  Rui Pan ,  Mohan Kumar Sudhakar ,  Brendan Hall

IPC: B41J2/045

Abstract: In some examples, a system includes a plurality of fluid ejection devices, a fluid ejection controller, and a plurality of data lines shared by the plurality of fluid ejection devices and connected between the fluid ejection controller and the plurality of fluid ejection devices. A first data line of the plurality of data lines communicates data of a first memory of a first fluid ejection device of the plurality of fluid ejection devices, and a second data line of the plurality of data lines communicates data of a second memory of the first fluid ejection device.

公开(公告)号：US11351776B2

公开(公告)日：2022-06-07

申请号：US16479822

申请日：2017-07-06

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Boon Bing Ng ,  Rui Pan ,  Mohan Kumar Sudhakar ,  Brendan Hall

IPC: B41J2/045 ,  B41J2/01

Abstract: In some examples, a circuit for use with a memory element and a nozzle for outputting fluid, includes a data line, a fire line, and a selector responsive to the data line to select the memory element or the nozzle. The selector is to select the memory element responsive to the data line having a first value, and to select the nozzle responsive to the data line having a second value different from the first value. The fire line is to control activation of the nozzle in response to the nozzle being selected by the selector, and to communicate data of the memory element in response to the memory element being selected by the selector.

公开(公告)号：US11642883B2

公开(公告)日：2023-05-09

申请号：US17806332

申请日：2022-06-10

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Boon Bing Ng ,  Rui Pan ,  Mohan Kumar Sudhakar ,  Brendan Hall

IPC: B41J2/045 ,  B41J2/01

CPC classification number: B41J2/0455 ,  B41J2/0458 ,  B41J2/04521 ,  B41J2/04541 ,  B41J2/04581 ,  B41J2/01 ,  B41J2/0452 ,  B41J2202/17

Abstract: In some examples, a circuit includes a data line, an input line, a first memory element, and a decoder to receive an address and to enable the first memory element for access in response to the address. The selector is responsive to the data line to select the first memory element, where the selector is to select the first memory element responsive to the data line having a first value, and where the data line is to communicate data of a second memory element in response to the second memory element being enabled for access. The input line is to communicate data of the first memory element in response to the first memory element being selected by the selector.

公开(公告)号：US20220297423A1

公开(公告)日：2022-09-22

申请号：US17806332

申请日：2022-06-10

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Boon Bing Ng ,  Rui Pan ,  Mohan Kumar Sudhakar ,  Brendan Hall

IPC: B41J2/045

Abstract: In some examples, a circuit includes a data line, an input line, a first memory element, and a decoder to receive an address and to enable the first memory element for access in response to the address. The selector is responsive to the data line to select the first memory element, where the selector is to select the first memory element responsive to the data line having a first value, and where the data line is to communicate data of a second memory element in response to the second memory element being enabled for access. The input line is to communicate data of the first memory element in response to the first memory element being selected by the selector.

公开(公告)号：US11364717B2

公开(公告)日：2022-06-21

申请号：US17454069

申请日：2021-11-09

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Boon Bing Ng ,  Rui Pan ,  Mohan Kumar Sudhakar ,  Brendan Hall

IPC: B41J2/045 ,  B41J2/01

Abstract: In some examples, a circuit includes a data line, an input line, a first memory element, and a decoder to receive an address and to enable the first memory element for access in response to the address. The selector is responsive to the data line to select the first memory element, where the selector is to select the first memory element responsive to the data line having a first value, and where the data line is to communicate data of a second memory element in response to the second memory element being enabled for access. The input line is to communicate data of the first memory element in response to the first memory element being selected by the selector.

公开(公告)号：US11090926B2

公开(公告)日：2021-08-17

申请号：US16608061

申请日：2017-07-06

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Boon Bing Ng ,  Rui Pan ,  Mohan Kumar Sudhakar ,  Hang Ru Goy

IPC: B41J2/045

Abstract: In some examples, a circuit for use with a fluid ejection device includes a plurality of decoders responsive to a common address to activate respective control signals at different times for selecting respective memories of the fluid ejection device. Each respective decoder of the plurality of decoders comprising a discharge switch to deactivate a control signal of the respective decoder while another decoder of the plurality of decoders is activating a control signal in response to the common address.

公开(公告)号：US20210354444A1

公开(公告)日：2021-11-18

申请号：US16479822

申请日：2017-07-06

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： Boon Bing Ng ,  Rui Pan ,  Mohan Kumar Sudhakar ,  Brendan Hall

IPC: B41J2/045

Abstract: In some examples, a circuit for use with a memory element and a nozzle for outputting fluid, includes a data line, a fire line, and a selector responsive to the data line to select the memory element or the nozzle. The selector is to select the memory element responsive to the data line having a first value, and to select the nozzle responsive to the data line having a second value different from the first value. The fire line is to control activation of the nozzle in response to the nozzle being selected by the selector, and to communicate data of the memory element in response to the memory element being selected by the selector.