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    PRINT COMPONENT WITH MEMORY CIRCUIT
    2.
    发明申请
    PRINT COMPONENT WITH MEMORY CIRCUIT 有权

    公开(公告)号：US20210237434A1

    公开(公告)日：2021-08-05

    申请号：US16768541

    申请日：2019-07-31

    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

    Inventor： Boon Bing NG ,  James Michael GARDNER ,  Scott A. LINN

    IPC: B41J2/045

    Abstract: A memory circuit for a print component including a plurality of I/O pads, including an analog pad, to connect to a plurality of signal paths which communicate operating signals to the print component. The memory circuit includes a controllable selector connected in line with one of the signal paths via the I/O pads, the selector controllable to disconnect the corresponding signal path to the print component, and a memory component to store memory values associated with the print component. A control circuit, in response to a sequence of operating signals received by the I/O pads representing a memory read, to operate the controllable selector to disconnect the signal path to the print component to block the memory read of the print component, and provide an analog signal to the analog pad to provide an analog electrical value at the analog pad representing stored memory values selected by the memory read.

    DECODERS FOR MEMORIES OF FLUID EJECTION DEVICES
    4.
    发明申请
    DECODERS FOR MEMORIES OF FLUID EJECTION DEVICES 有权

    公开(公告)号：US20210094281A1

    公开(公告)日：2021-04-01

    申请号：US16608061

    申请日：2017-07-06

    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

    Inventor： Boon Bing NG ,  Rui Pan ,  Mohan Kumar Sudhakar ,  Hang Ru Goy

    IPC: B41J2/045

    Abstract: In some examples, a circuit for use with a fluid ejection device includes a plurality of decoders responsive to a common address to activate respective control signals at different times for selecting respective memories of the fluid ejection device. Each respective decoder of the plurality of decoders comprising a discharge switch to deactivate a control signal of the respective decoder while another decoder of the plurality of decoders is activating a control signal in response to the common address.

    FLUID EJECTION DEVICES INCLUDING A MEMORY
    5.
    发明申请
    FLUID EJECTION DEVICES INCLUDING A MEMORY 有权

    公开(公告)号：US20210252852A1

    公开(公告)日：2021-08-19

    申请号：US16959085

    申请日：2019-04-19

    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

    Inventor： Boon Bing NG ,  Mohan Kumar SUDHAKAR

    IPC: B41J2/045

    Abstract: An integrated circuit to drive a plurality of fluid actuation devices includes an ID line, a fire line, a discharge path, a memory element, and a latch. The memory element is electrically coupled to the fire line and the discharge path. The latch disables the discharge path in response to a first logic level on the ID line and enables the discharge path in response to a second logic level on the ID line.

    PRINT COMPONENT WITH MEMORY CIRCUIT
    6.
    发明申请
    PRINT COMPONENT WITH MEMORY CIRCUIT 有权

    公开(公告)号：US20210206164A1

    公开(公告)日：2021-07-08

    申请号：US16768096

    申请日：2019-07-31

    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

    Inventor： James Michael GARDNER ,  Boon Bing NG

    IPC: B41J2/045 ,  G06F3/12

    Abstract: A memory circuit for a print component including a plurality of I/O pads, including an analog pad, to connect to a plurality of signal paths which communicate operating signals to the print component. A memory component stores memory values associated with the print component, and a control circuit, in response to a sequence of operating signals on the I/O pads representing a memory read, provides an analog signal to the analog pad to provide an analog electrical value at the analog pad representing stored memory values selected by the memory read.

    PRINT COMPONENT WITH MEMORY CIRCUIT
    8.
    发明申请
    PRINT COMPONENT WITH MEMORY CIRCUIT 有权

    公开(公告)号：US20220379602A1

    公开(公告)日：2022-12-01

    申请号：US17884329

    申请日：2022-08-09

    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

    Inventor： Boon Bing NG ,  James Michael GARDNER

    IPC: B41J2/045

    Abstract: A memory circuit for a print component including a plurality of I/O pads, including an analog pad, to connect to a plurality of signals paths which communicate operating signals to the print component, and a memory component to store memory values associated with the print component. A control circuit to, in response to identifying a sequence of operating signals representing a memory read, provide a first analog signal on the analog pad in parallel with a second analog signal from the print component to provide an analog electrical value on the analog pad representing stored memory values selected by the memory read.

    PRINT COMPONENT WITH MEMORY CIRCUIT
    9.
    发明申请
    PRINT COMPONENT WITH MEMORY CIRCUIT 有权

    公开(公告)号：US20210316550A1

    公开(公告)日：2021-10-14

    申请号：US16768588

    申请日：2019-07-31

    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

    Inventor： James Michael GARDNER ,  Boon Bing NG

    IPC: B41J2/045 ,  G11C7/10 ,  G06F13/16

    Abstract: A memory circuit for a print component including plurality of I/O pads, including a first analog pad and a second analog pad, to connect to a plurality of signal paths which communicate operating signals to the print component, including an analog signal path connected to the first analog pad and the second analog pad, the first analog pad electrically isolated from the second analog pad to interrupt the analog signal path to the print component. The memory circuit further includes a memory component to store memory values associated with the print component, and a control circuit to, in response to a sequence of operating signals received by the I/O pads representing a memory read, provide an analog signal to the analog pad to provide an analog electrical value at the analog pad representing stored memory values selected by the memory read.

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