-
1.发明申请SYSTEM AND METHOD FOR ACCOMMODATING NON-GAUSSIAN AND NON-LINEAR SOURCES OF VARIATION IN STATISTICAL STATIC TIMING ANALYSIS 有权统计静态时序分析中非GAUSSIAN和非线性变量源变化的系统与方法公开(公告)号：US20080201676A1
公开(公告)日：2008-08-21
申请号：US12114203
申请日：2008-05-02
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： There is provided a system and method for statistical timing analysis and optimization of an electrical circuit having two or more digital elements. The system includes at least one parameter input and a statistical static timing analyzer and electrical circuit optimizer. The at least one parameter input is for receiving parameters of the electrical circuit. At least one of the parameters has at least one of a non-Gaussian probability distribution and a non-linear delay effect. The statistical static timing analyzer and electrical circuit optimizer is for calculating at least one of a signal arrival time and a signal required time for the electrical circuit using the at least one parameter and for modifying a component size of the electrical circuit to alter gate timing characteristics of the electrical circuit based upon the at least one of the signal arrival time and the signal required time.
摘要翻译： 提供了一种用于具有两个或多个数字元件的电路的统计时序分析和优化的系统和方法。 该系统包括至少一个参数输入和统计静态时序分析器和电路优化器。 至少一个参数输入用于接收电路的参数。 至少一个参数具有非高斯概率分布和非线性延迟效应中的至少一个。 统计静态时序分析器和电路优化器用于使用至少一个参数来计算电路的信号到达时间和信号所需时间中的至少一个，并且用于修改电路的组件尺寸以改变门时序特性 基于信号到达时间和信号所需时间中的至少一个。
-
2.发明申请SYSTEM AND METHOD FOR ACCOMMODATING NON-GAUSSIAN AND NON-LINEAR SOURCES OF VARIATION IN STATISTICAL STATIC TIMING ANALYSIS 审中-公开统计静态时序分析中非GAUSSIAN和非线性变量源变化的系统与方法公开(公告)号：US20070234256A1
公开(公告)日：2007-10-04
申请号：US11762405
申请日：2007-06-13
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： There is provided a system and method for statistical timing analysis and optimization of an electrical circuit having two or more digital elements. The system includes at least one parameter input and a statistical static timing analyzer and electrical circuit optimizer. The at least one parameter input is for receiving parameters of the electrical circuit. At least one of the parameters has at least one of a non-Gaussian probability distribution and a non-linear delay effect. The statistical static timing analyzer and electrical circuit optimizer is for calculating at least one of a signal arrival time and a signal required time for the electrical circuit using the at least one parameter and for modifying a component size of the electrical circuit to alter gate timing characteristics of the electrical circuit based upon the at least one of the signal arrival time and the signal required time.
摘要翻译： 提供了一种用于具有两个或多个数字元件的电路的统计时序分析和优化的系统和方法。 该系统包括至少一个参数输入和统计静态时序分析器和电路优化器。 至少一个参数输入用于接收电路的参数。 至少一个参数具有非高斯概率分布和非线性延迟效应中的至少一个。 统计静态时序分析器和电路优化器用于使用至少一个参数来计算电路的信号到达时间和信号所需时间中的至少一个，并且用于修改电路的组件尺寸以改变门时序特性 基于信号到达时间和信号所需时间中的至少一个。
-
3.发明授权System and method for accommodating non-Gaussian and non-linear sources of variation in statistical static timing analysis 有权用于在统计静态时序分析中适应非高斯和非线性变化源的系统和方法公开(公告)号：US07293248B2
公开(公告)日：2007-11-06
申请号：US11056850
申请日：2005-02-11
CPC分类号： G06F17/5031
摘要： There is provided a system and method for statistical timing analysis of an electrical circuit. The system includes at least one parameter input, a statistical static timing analyzer, and at least one output. The at least one parameter input is for receiving parameters of the electrical circuit. At least one of the parameters has at least one of a non-Gaussian probability distribution and a non-linear delay effect. The statistical static timing analyzer is for calculating at least one of a signal arrival time and a signal required time for the electrical circuit using the at least one parameter. The at least one output is for outputting the at least one of the signal arrival time and the signal required time.
摘要翻译： 提供了一种用于电路的统计时序分析的系统和方法。 该系统包括至少一个参数输入，统计静态时序分析器和至少一个输出。 至少一个参数输入用于接收电路的参数。 至少一个参数具有非高斯概率分布和非线性延迟效应中的至少一个。 统计静态时序分析器用于使用至少一个参数来计算电路的信号到达时间和信号所需时间中的至少一个。 至少一个输出用于输出信号到达时间和信号所需时间中的至少一个。
-
4.发明申请System and method for accommodating non-gaussian and non-linear sources of variation in statistical static timing analysis 有权用于在统计静态时序分析中调节非高斯和非线性变化源的系统和方法公开(公告)号：US20060085775A1
公开(公告)日：2006-04-20
申请号：US11056850
申请日：2005-02-11
CPC分类号： G06F17/5031
摘要： There is provided a system and method for statistical timing analysis of an electrical circuit. The system includes at least one parameter input, a statistical static timing analyzer, and at least one output. The at least one parameter input is for receiving parameters of the electrical circuit. At least one of the parameters has at least one of a non-Gaussian probability distribution and a non-linear delay effect. The statistical static timing analyzer is for calculating at least one of a signal arrival time and a signal required time for the electrical circuit using the at least one parameter. The at least one output is for outputting the at least one of the signal arrival time and the signal required time.
摘要翻译： 提供了一种用于电路的统计时序分析的系统和方法。 该系统包括至少一个参数输入，统计静态时序分析器和至少一个输出。 至少一个参数输入用于接收电路的参数。 至少一个参数具有非高斯概率分布和非线性延迟效应中的至少一个。 统计静态时序分析器用于使用至少一个参数来计算电路的信号到达时间和信号所需时间中的至少一个。 至少一个输出用于输出信号到达时间和信号所需时间中的至少一个。
-
5.发明授权System and method for accommodating non-gaussian and non-linear sources of variation in statistical static timing analysis 有权用于在统计静态时序分析中调节非高斯和非线性变化源的系统和方法公开(公告)号：US08015525B2
公开(公告)日：2011-09-06
申请号：US12114203
申请日：2008-05-02
CPC分类号： G06F17/5031
摘要： There is provided a system and method for statistical timing analysis and optimization of an electrical circuit having two or more digital elements. The system includes at least one parameter input and a statistical static timing analyzer and electrical circuit optimizer. The at least one parameter input is for receiving parameters of the electrical circuit. At least one of the parameters has at least one of a non-Gaussian probability distribution and a non-linear delay effect. The statistical static timing analyzer and electrical circuit optimizer is for calculating at least one of a signal arrival time and a signal required time for the electrical circuit using the at least one parameter and for modifying a component size of the electrical circuit to alter gate timing characteristics of the electrical circuit based upon the at least one of the signal arrival time and the signal required time.
摘要翻译： 提供了一种用于具有两个或多个数字元件的电路的统计时序分析和优化的系统和方法。 该系统包括至少一个参数输入和统计静态时序分析器和电路优化器。 至少一个参数输入用于接收电路的参数。 至少一个参数具有非高斯概率分布和非线性延迟效应中的至少一个。 统计静态时序分析器和电路优化器用于使用至少一个参数来计算电路的信号到达时间和信号所需时间中的至少一个，并且用于修改电路的组件尺寸以改变门时序特性 基于信号到达时间和信号所需时间中的至少一个。
-
公开(公告)号：US08781792B2
公开(公告)日：2014-07-15
申请号：US12610291
申请日：2009-10-31
IPC分类号： G06F11/30
CPC分类号： G06F17/5045 , G06F2217/10 , G06F2217/82
摘要： Techniques for improving parametric chip yield of manufactured chips are provided. In one aspect, a method for optimizing parametric chip yield is provided. The method includes the following steps. Parametric chip yield is computed based on performance and power consumption of a plurality of manufactured chips subject to a given voltage binning scheme. It is then determined whether the parametric chip yield computed is optimal. If the parametric chip yield is not optimal, the voltage binning scheme is altered and the compute and determine steps are repeated. Otherwise the binning scheme is left unaltered.
摘要翻译： 提供了用于提高制造芯片的参数芯片产量的技术。 在一方面，提供了一种用于优化参数芯片产量的方法。 该方法包括以下步骤。 基于经受给定电压合并方案的多个制造的芯片的性能和功耗来计算参数芯片产量。 然后确定计算的参数芯片产量是否是最佳的。 如果参数芯片产量不是最优的，则改变电压组合方案，并重复计算和确定步骤。 否则，binning方案保持不变。
-
7.发明授权Performing statistical timing analysis with non-separable statistical and deterministic variations 失效用不可分的统计和确定性变化进行统计时序分析公开(公告)号：US08418107B2
公开(公告)日：2013-04-09
申请号：US12943541
申请日：2010-11-10
申请人： Jeffrey G Hemmett , Debjit Sinha , Natesan Venkateswaran , Chandramouli Visweswariah , Vladimir Zolotov
发明人： Jeffrey G Hemmett , Debjit Sinha , Natesan Venkateswaran , Chandramouli Visweswariah , Vladimir Zolotov
CPC分类号： G06F17/504 , G06F2217/10 , G06F2217/84
摘要： In one embodiment, the invention is a method and apparatus for performing statistical timing analysis with non-separable statistical and deterministic variations. One embodiment of a method for performing timing analysis of an integrated circuit chip includes computing delays and slews of chip gates and wires, wherein the delays and slews depend on at least a first process parameter that is deterministic and corner-based and a second process parameter that is statistical and non-separable with the first process parameter, and performing a single timing run using the timing quantity, wherein the single timing run produces arrival times, required arrival times, and timing slacks at outputs, latches, and circuit nodes of the integrated circuit chip. The computed arrival times, required arrival times, and timing slacks can be projected to a corner value of deterministic variations in order to obtain a statistical model of the delays and stews at the corresponding corner.
摘要翻译： 在一个实施例中，本发明是用于以不可分的统计和确定性变化执行统计时序分析的方法和装置。 用于执行集成电路芯片的定时分析的方法的一个实施例包括计算芯片栅极和导线的延迟和压摆，其中所述延迟和压摆取决于至少一个确定性和基于角的第一工艺参数，以及第二工艺参数 其与第一过程参数是统计的且不可分离的，并且使用定时数量执行单个定时运行，其中单个定时运行产生到达时间，所需的到达时间和定时偏移在输出，锁存器和电路节点 集成电路芯片。 计算的到达时间，所需的到达时间和时间休息可以被计算为确定性变化的角落值，以便获得相应角落处的延迟和炖菜的统计模型。
-
8.发明申请Method of Measuring the Impact of Clock Skew on Slack During a Statistical Static Timing Analysis 有权在统计静态时序分析中测量时钟偏移对松弛影响的方法公开(公告)号：US20120047477A1
公开(公告)日：2012-02-23
申请号：US12857591
申请日：2010-08-17
CPC分类号： G06F17/5031 , G06F2217/84
摘要： Computing accurately and effectively the impact of clock skew on statistical slack in the presence of statistically variable timing quantities that accounts for both common path credit in the common portion of the clock tree, and RSS credit in the non-common of the clock tree. The clock skew is measured on a per launch and capture path-pair basis as a function of on the post-CPPR path-specific slack (including RSS credit), total mean value of latch-to-latch delay, RSS value of random latch-to-latch delay, test guard time and test adjust. The method includes: performing an initial block-based SSTA including CPPR analysis; selecting at least one launch and capture path-pair for skew analysis; for the at least one path pair, recording post CPPR slack, total mean value of latch-to-latch delay, RSS value of latch to latch delay, test guard time and test adjust; and quantifying the impact of clock skew on statistical slack thereof.
摘要翻译： 计算时钟偏差对统计松弛的影响，存在统计上可变的时序量，这些时间量占时钟树共同部分的公共路径信誉，以及时钟树非共同的RSS信用。 时钟偏移在每个发射和捕获路径对的基础上测量，作为后CPPR路径特定松弛（包括RSS信用），锁存到锁存延迟的总平均值，随机锁存的RSS值的函数 到锁定延迟，测试保护时间和测试调整。 该方法包括：执行初始的基于块的SSTA，包括CPPR分析; 选择至少一个启动和捕获路径对进行偏差分析; 对于至少一个路径对，记录后CPPR松弛，锁存到锁存延迟的总平均值，锁存器的RSS值到锁存延迟，测试保护时间和测试调整; 并量化时钟偏移对其统计松弛的影响。
-
9.发明申请公开(公告)号：US20110106483A1
公开(公告)日：2011-05-05
申请号：US12610090
申请日：2009-10-30
CPC分类号： G01R31/31835
摘要： In one embodiment, the invention is a method and apparatus for selecting paths for use in at-speed testing. One embodiment of a method for selecting a set of n paths with which to test an integrated circuit chip includes: organizing the set of n paths into a plurality of sub-sets, receiving a new candidate path, and adding the new candidate path to one of the sub-sets when the new candidate path improves the process coverage metric of the sub-sets.
摘要翻译： 在一个实施例中，本发明是用于选择在速度测试中使用的路径的方法和装置。 用于选择用于测试集成电路芯片的n个路径的集合的方法的一个实施例包括：将n个路径的集合组织成多个子集，接收新的候选路径，并将新的候选路径添加到一个 当新的候选路径改进子集的过程覆盖度量时，子集的子集。
-
10.发明授权Representing and propagating a variational voltage waveform in statistical static timing analysis of digital circuits 有权在数字电路的统计静态时序分析中表征和传播变分电压波形公开(公告)号：US07814448B2
公开(公告)日：2010-10-12
申请号：US11733058
申请日：2007-04-09
申请人： Soroush Abbaspour , David J. Hathaway , Chandramouli Visweswariah , Jinjun Xiong , Vladimir Zolotov
发明人： Soroush Abbaspour , David J. Hathaway , Chandramouli Visweswariah , Jinjun Xiong , Vladimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： An approach that represents and propagates a variational voltage waveform in statistical static timing analysis of digital circuits is described. In one embodiment, there is a statistical static timing analysis tool for analyzing digital circuit designs. The statistical static timing analysis tool includes a variational waveform modeling component that is configured to generate a variational waveform model that approximate arbitrary waveform transformations of waveforms at nodes of a digital circuit. The variational waveform model transforms a nominal waveform into a perturbed waveform in accordance with a plurality of waveform transformation operators that account for variations that occur between the nominal waveform and the perturbed waveform. A variational waveform propagating component is configured to propagate variational waveforms through a timing arc from at least one input to at least one output of the digital circuit in accordance with the variational waveform model.
摘要翻译： 描述了在数字电路的统计静态时序分析中表示和传播变化电压波形的方法。 在一个实施例中，存在用于分析数字电路设计的统计静态时序分析工具。 统计静态时序分析工具包括变分波形建模组件，其被配置为生成近似波形在数字电路节点处的任意波形变换的变分波形模型。 变分波形模型根据考虑在标称波形和扰动波形之间出现的变化的多个波形变换算子将标称波形变换为扰动波形。 变分波形传播分量被配置为根据变化波形模型将变化波形传播通过定时弧从数字电路的至少一个输入到至少一个输出。
-
-
-
-
-
-
-
-
-
搜索结果
64 条记录 (耗时 0.025 秒)
