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    Method of measuring the impact of clock skew on slack during a statistical static timing analysis
    2.
    发明授权
    Method of measuring the impact of clock skew on slack during a statistical static timing analysis 有权
    在统计静态时序分析期间测量时钟偏移对松弛影响的方法

    公开(公告)号：US08578310B2

    公开(公告)日：2013-11-05

    申请号：US12857591

    申请日：2010-08-17

    申请人： Kerim Kalafala ,  Natesan Venkateswaran ,  Chandramouli Visweswariah ,  Vladimir Zolotov

    发明人： Kerim Kalafala ,  Natesan Venkateswaran ,  Chandramouli Visweswariah ,  Vladimir Zolotov

    IPC分类号： G06F9/455 ,  G06F17/50

    CPC分类号： G06F17/5031 ,  G06F2217/84

    摘要： Computing accurately and effectively the impact of clock skew on statistical slack in the presence of statistically variable timing quantities that accounts for both common path credit in the common portion of the clock tree, and RSS credit in the non-common of the clock tree. The clock skew is measured on a per launch and capture path-pair basis as a function of on the post-CPPR path-specific slack (including RSS credit), total mean value of latch-to-latch delay, RSS value of random latch-to-latch delay, test guard time and test adjust. The method includes: performing an initial block-based SSTA including CPPR analysis; selecting at least one launch and capture path-pair for skew analysis; for the at least one path pair, recording post CPPR slack, total mean value of latch-to-latch delay, RSS value of latch to latch delay, test guard time and test adjust; and quantifying the impact of clock skew on statistical slack thereof.

    摘要翻译： 计算时钟偏差对统计松弛的影响，存在统计上可变的时序量，这些时间量占时钟树共同部分的公共路径信誉，以及时钟树非共同的RSS信用。 时钟偏移在每个发射和捕获路径对的基础上测量，作为后CPPR路径特定松弛（包括RSS信用），锁存到锁存延迟的总平均值，随机锁存的RSS值的函数 到锁定延迟，测试保护时间和测试调整。 该方法包括：执行初始的基于块的SSTA，包括CPPR分析; 选择至少一个启动和捕获路径对进行​​偏差分析; 对于至少一个路径对，记录后CPPR松弛，锁存到锁存延迟的总平均值，锁存器的RSS值到锁存延迟，测试保护时间和测试调整; 并量化时钟偏移对其统计松弛的影响。

    Method of Measuring the Impact of Clock Skew on Slack During a Statistical Static Timing Analysis
    4.
    发明申请
    Method of Measuring the Impact of Clock Skew on Slack During a Statistical Static Timing Analysis 有权
    在统计静态时序分析中测量时钟偏移对松弛影响的方法

    公开(公告)号：US20120047477A1

    公开(公告)日：2012-02-23

    申请号：US12857591

    申请日：2010-08-17

    申请人： Kerim Kalafala ,  Natesan Venkateswaran ,  Chandramouli Visweswariah ,  Vladimir Zolotov

    发明人： Kerim Kalafala ,  Natesan Venkateswaran ,  Chandramouli Visweswariah ,  Vladimir Zolotov

    IPC分类号： G06F9/455 ,  G06F17/50

    CPC分类号： G06F17/5031 ,  G06F2217/84

    摘要： Computing accurately and effectively the impact of clock skew on statistical slack in the presence of statistically variable timing quantities that accounts for both common path credit in the common portion of the clock tree, and RSS credit in the non-common of the clock tree. The clock skew is measured on a per launch and capture path-pair basis as a function of on the post-CPPR path-specific slack (including RSS credit), total mean value of latch-to-latch delay, RSS value of random latch-to-latch delay, test guard time and test adjust. The method includes: performing an initial block-based SSTA including CPPR analysis; selecting at least one launch and capture path-pair for skew analysis; for the at least one path pair, recording post CPPR slack, total mean value of latch-to-latch delay, RSS value of latch to latch delay, test guard time and test adjust; and quantifying the impact of clock skew on statistical slack thereof.

    摘要翻译： 计算时钟偏差对统计松弛的影响，存在统计上可变的时序量，这些时间量占时钟树共同部分的公共路径信誉，以及时钟树非共同的RSS信用。 时钟偏移在每个发射和捕获路径对的基础上测量，作为后CPPR路径特定松弛（包括RSS信用），锁存到锁存延迟的总平均值，随机锁存的RSS值的函数 到锁定延迟，测试保护时间和测试调整。 该方法包括：执行初始的基于块的SSTA，包括CPPR分析; 选择至少一个启动和捕获路径对进行​​偏差分析; 对于至少一个路径对，记录后CPPR松弛，锁存到锁存延迟的总平均值，锁存器的RSS值到锁存延迟，测试保护时间和测试调整; 并量化时钟偏移对其统计松弛的影响。

    Performing a statistical timing abstraction for a hierarchical timing analysis of VLSI circuits
    5.
    发明授权
    Performing a statistical timing abstraction for a hierarchical timing analysis of VLSI circuits 有权
    对VLSI电路的分层定时分析执行统计时序抽象

    公开(公告)号：US08122404B2

    公开(公告)日：2012-02-21

    申请号：US12388932

    申请日：2009-02-19

    申请人： Debjit Sinha ,  Adil Bhanji ,  Barry L. Dorfman ,  Kerim Kalafala ,  Natesan Venkateswaran ,  Chandramouli Visweswariah

    发明人： Debjit Sinha ,  Adil Bhanji ,  Barry L. Dorfman ,  Kerim Kalafala ,  Natesan Venkateswaran ,  Chandramouli Visweswariah

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5031

    摘要： A method for performing a hierarchical statistical timing analysis of an integrated circuit (IC) chip design by abstracting one or more macros of the design. The method includes performing a statistical static timing analysis of at least one macro; performing a statistical abstraction of the macro to obtain a statistical abstract model of the macro timing characteristics; applying the statistical abstract model as the timing model for each occurrence of the macro leading to a simplified IC chip design; and performing a hierarchical statistical timing analysis of the simplified chip design. The method achieves a context aware statistical abstraction, where a generated statistical abstract model is instantiated for each macro of the chip during statistical static timing analysis at the chip level, providing a compressed and pruned statistical timing abstraction and reducing the model-size during the statistical abstraction.

    摘要翻译： 一种用于通过抽象设计的一个或多个宏来执行集成电路（IC）芯片设计的分层统计时序分析的方法。 该方法包括执行至少一个宏的统计静态时序分析; 执行宏的统计抽象以获得宏定时特征的统计抽象模型; 将统计抽象模型应用于宏观出现的时序模型，从而实现简化的IC芯片设计; 并执行简化芯片设计的分层统计时序分析。 该方法实现上下文感知统计抽象，其中在芯片级的统计静态时序分析期间为芯片的每个宏实例化生成的统计抽象模型，提供压缩和修剪的统计时序抽象并且在统计期间减小模型大小 抽象。

    Method of Performing Statistical Timing Abstraction for Hierarchical Timing Analysis of VLSI circuits
    6.
    发明申请
    Method of Performing Statistical Timing Abstraction for Hierarchical Timing Analysis of VLSI circuits 有权
    执行VLSI电路分层时序分析的统计时序抽象方法

    公开(公告)号：US20100211922A1

    公开(公告)日：2010-08-19

    申请号：US12388932

    申请日：2009-02-19

    申请人： Debjit Sinha ,  Adil Bhanji ,  Barry L. Dorfman ,  Kerim Kalafala ,  Natesan Venkateswaran ,  Chandramouli Visweswariah

    发明人： Debjit Sinha ,  Adil Bhanji ,  Barry L. Dorfman ,  Kerim Kalafala ,  Natesan Venkateswaran ,  Chandramouli Visweswariah

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5031

    摘要： A method for performing a hierarchical statistical timing analysis of an integrated circuit (IC) chip design by abstracting one or more macros of the design. The method includes performing a statistical static timing analysis of at least one macro; performing a statistical abstraction of the macro to obtain a statistical abstract model of the macro timing characteristics; applying the statistical abstract model as the timing model for each occurrence of the macro leading to a simplified IC chip design; and performing a hierarchical statistical timing analysis of the simplified chip design. The method achieves a context aware statistical abstraction, where a generated statistical abstract model is instantiated for each macro of the chip during statistical static timing analysis at the chip level, providing a compressed and pruned statistical timing abstraction and reducing the model-size during the statistical abstraction.

    摘要翻译： 一种用于通过抽象设计的一个或多个宏来执行集成电路（IC）芯片设计的分层统计时序分析的方法。 该方法包括执行至少一个宏的统计静态时序分析; 执行宏的统计抽象以获得宏定时特征的统计抽象模型; 将统计抽象模型应用于宏观出现的时序模型，从而实现简化的IC芯片设计; 并执行简化芯片设计的分层统计时序分析。 该方法实现上下文感知统计抽象，其中在芯片级的统计静态时序分析期间为芯片的每个宏实例化生成的统计抽象模型，提供压缩和修剪的统计时序抽象并且在统计期间减小模型大小 抽象。

    METHOD AND SYSTEM FOR EVALUATING STATISTICAL SENSITIVITY CREDIT IN PATH-BASED HYBRID MULTI-CORNER STATIC TIMING ANALYSIS
    7.
    发明申请
    METHOD AND SYSTEM FOR EVALUATING STATISTICAL SENSITIVITY CREDIT IN PATH-BASED HYBRID MULTI-CORNER STATIC TIMING ANALYSIS 失效
    基于路径的混合多角度静态时序分析评估统计灵敏度信息的方法和系统

    公开(公告)号：US20080209373A1

    公开(公告)日：2008-08-28

    申请号：US11679251

    申请日：2007-02-27

    申请人： Nathan C. Buck ,  John P. Dubuque ,  Eric A. Foreman ,  Peter A. Habitz ,  Kerim Kalafala ,  Peihua Qi ,  Chandramouli Visweswariah ,  Xiaoyue Wang

    发明人： Nathan C. Buck ,  John P. Dubuque ,  Eric A. Foreman ,  Peter A. Habitz ,  Kerim Kalafala ,  Peihua Qi ,  Chandramouli Visweswariah ,  Xiaoyue Wang

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5031

    摘要： Methods, systems and computer program products for analyzing a timing design of an integrated circuit are disclosed. According to an embodiment, a method for analyzing a timing design of an integrated circuit comprises: providing an initial static timing analysis of the integrated circuit; selecting a static timing test with respect to a static timing test point based on the initial static timing analysis; selecting a timing path leading to the static timing test point for the static timing test; determining an integrated slack path variability for the timing path based on a joint probability distribution of at least one statistically independent parameter; and analyzing the timing design based on the integrated slack path variability.

    摘要翻译： 公开了用于分析集成电路的定时设计的方法，系统和计算机程序产品。 根据实施例，用于分析集成电路的定时设计的方法包括：提供集成电路的初始静态时序分析; 基于初始静态时序分析，选择静态定时测试点的静态定时测试; 选择通过静态定时测试的静态定时测试点的定时路径; 基于至少一个统计学独立参数的联合概率分布来确定所述定时路径的综合松弛路径可变性; 并基于综合的松弛路径变异性分析时序设计。

    AFFINITY-BASED CLUSTERING OF VECTORS FOR PARTITIONING THE COLUMNS OF A MATRIX
    8.
    发明申请
    AFFINITY-BASED CLUSTERING OF VECTORS FOR PARTITIONING THE COLUMNS OF A MATRIX 有权
    用于分割矩阵列的矢量的基于亲和度的聚类

    公开(公告)号：US20080140983A1

    公开(公告)日：2008-06-12

    申请号：US12020879

    申请日：2008-01-28

    申请人： Kerim Kalafala ,  Vasant Rao ,  Chandramouli Visweswariah

    发明人： Kerim Kalafala ,  Vasant Rao ,  Chandramouli Visweswariah

    IPC分类号： G06F12/02

    CPC分类号： G06F17/5031 ,  G06K9/6226 ,  G06K9/6247

    摘要： A computer system for partitioning the columns of a matrix A. The computer system includes a processor and a memory unit coupled to the processor. Program code in the memory unit, when executed by the processor, implements the method. Matrix A is provided in a memory device and has n columns and m rows; wherein n is an integer of at least 3; and wherein m is an integer of at least 1. The n columns is partitioned into a closed group of p clusters, p being a positive integer of at least 2 and less than n. The partitioning includes an affinity-based merging of clusters of pairs of clusters of the matrix A based on an affinity between the clusters in each pair of clusters being merged. Each cluster consists of one or more columns of matrix A. The p clusters are stored in a computer-readable storage device.

    摘要翻译： 一种用于分割矩阵A的列的计算机系统。计算机系统包括处理器和耦合到处理器的存储器单元。 当处理器执行时，存储器单元中的程序代码实现该方法。 矩阵A在存储器件中提供并具有n列和m行; 其中n为至少3的整数; 并且其中m是至少为1的整数。n列被划分成闭合的p个簇，p是至少为2且小于n的正整数。 基于被合并的每对簇中的簇之间的亲和度，分割包括矩阵A的聚类对的聚类的基于亲和度的合并。 每个簇由矩阵A的一个或多个列组成.P个簇存储在计算机可读存储设备中。

    AFFINITY-BASED CLUSTERING OF VECTORS FOR PARTITIONING THE COLUMNS OF A MATRIX
    9.
    发明申请
    AFFINITY-BASED CLUSTERING OF VECTORS FOR PARTITIONING THE COLUMNS OF A MATRIX 有权
    用于分割矩阵列的矢量的基于亲和度的聚类

    公开(公告)号：US20070276896A1

    公开(公告)日：2007-11-29

    申请号：US11836842

    申请日：2007-08-10

    申请人： Kerim Kalafala ,  Vasant Rao ,  Chandramouli Visweswariah

    发明人： Kerim Kalafala ,  Vasant Rao ,  Chandramouli Visweswariah

    IPC分类号： G06F7/32 ,  G06F17/50

    CPC分类号： G06F17/5031 ,  G06K9/6226 ,  G06K9/6247

    摘要： A method for partitioning the columns of a matrix A. The method includes providing the matrix A in a memory device of a computer system. The matrix A has n columns and m rows, wherein n is an integer of at least 3, and wherein m is an integer of at least 1. The method further includes executing an algorithm by a processor of the computer system. Executing the algorithm includes partitioning the n columns of the matrix A into a closed group of p clusters, wherein p is a positive integer of at least 2 and less than n, wherein the partitioning includes an affinity-based merging of clusters of the matrix A, and wherein each cluster is a collection of one or more columns of A.

    摘要翻译： 用于分割矩阵A的列的方法。该方法包括将矩阵A提供到计算机系统的存储器设备中。 矩阵A具有n列和m行，其中n是至少为3的整数，并且其中m是至少为1的整数。该方法还包括由计算机系统的处理器执行算法。 执行算法包括将矩阵A的n列划分成闭合的p个群集，其中p是至少为2且小于n的正整数，其中分区包括基于关系的矩阵A的簇的合并 ，并且其中每个聚类是A的一列或多列的集合。

    System and method for correlated process pessimism removal for static timing analysis
    10.
    发明授权
    System and method for correlated process pessimism removal for static timing analysis 失效
    静态时序分析相关过程悲观消除的系统和方法

    公开(公告)号：US07117466B2

    公开(公告)日：2006-10-03

    申请号：US10665273

    申请日：2003-09-18

    申请人： Kerim Kalafala ,  Peihua Qi ,  David J. Hathaway ,  Alexander J. Suess ,  Chandramouli Visweswariah

    发明人： Kerim Kalafala ,  Peihua Qi ,  David J. Hathaway ,  Alexander J. Suess ,  Chandramouli Visweswariah

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5031

    摘要： A method of removing pessimism in static timing analysis is described. Delays are expressed as a function of discrete parameter settings allowing for both local and global variation to be taken in to account. Based on a specified target slack, each failing timing test is examined to determine a consistent set of parameter settings which produces the worst possible slack. The analysis is performed on a path basis. By considering only parameters which are in common to a particular data/clock path-pair, the number of process combinations that need to be explored is reduced when compared to analyzing all combinations of the global parameter settings. Further, if parameters are separable and linear, worst-case variable assignments for a particular clock/data path pair can be computed in linear time by independently assigning each parameter value. In addition, if available, the incremental delay change with respect to each physically realizable process variable may be used to project the worst-case variable assignment on a per-path basis without the need for performing explicit corner enumeration.

    摘要翻译： 描述了静态时序分析中消除悲观情绪的方法。 延迟表示为离散参数设置的函数，允许将本地和全局变量都用于账户。 根据指定的目标松弛，检查每个失败的定时测试，以确定一组一致的参数设置，从而产生最差的松弛。 分析以路径为基础进行。 通过仅考虑与特定数据/时钟路径对共同的参数，与分析全局参数设置的所有组合相比，需要探索的进程组合的数量减少。 此外，如果参数是可分离的和线性的，则通过独立地分配每个参数值，可以在线性时间内计算特定时钟/数据路径对的最差情况变量分配。 另外，如果可用，可以使用相对于每个物理上可实现的过程变量的增量延迟变化来在每个路径基础上投射最坏情况的变量赋值，而不需要执行明确的角点枚举。