公开(公告)号：US11302786B2

公开(公告)日：2022-04-12

申请号：US16773090

申请日：2020-01-27

Applicant: HRL Laboratories, LLC

Inventor： Joel C. Wong ,  Jeong-Sun Moon ,  Robert M. Grabar ,  Michael T. Antcliffe

IPC: H01L29/40 ,  H01L29/20 ,  H01L29/205 ,  H01L29/41 ,  H01L29/423 ,  H01L29/66 ,  H01L21/285 ,  H01L21/311 ,  H01L21/765 ,  H01L29/778

Abstract: A method of fabricating a gate with a mini field plate includes forming a dielectric passivation layer over an epitaxy layer on a substrate, coating the dielectric passivation layer with a first resist layer, etching the first resist layer and the dielectric passivation layer to form a first opening in the dielectric passivation layer, removing the first resist layer, and forming a tri-layer gate having a gate foot in the first opening, a gate neck extending from the gate foot, and a gate head extending from the gate neck. The gate foot has a first width, and the gate neck has a second width that is wider than the first width. The gate neck extends for a length over the dielectric passivation layer on both sides of the first opening. The gate head has a third width wider than the second width of the gate neck.

公开(公告)号：US11764271B2

公开(公告)日：2023-09-19

申请号：US17684948

申请日：2022-03-02

Applicant: HRL Laboratories, LLC

Inventor： Joel C. Wong ,  Jeong-Sun Moon ,  Robert M. Grabar ,  Michael T. Antcliffe

IPC: H01L29/40 ,  H01L29/20 ,  H01L29/205 ,  H01L29/41 ,  H01L29/423 ,  H01L29/66 ,  H01L21/285 ,  H01L21/311 ,  H01L21/765 ,  H01L29/778

CPC classification number: H01L29/404 ,  H01L21/28587 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/765 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/413 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/7786

Abstract: A method of fabricating a gate with a mini field plate includes forming a dielectric passivation layer over an epitaxy layer on a substrate, coating the dielectric passivation layer with a first resist layer, etching the first resist layer and the dielectric passivation layer to form a first opening in the dielectric passivation layer, removing the first resist layer; and forming a tri-layer gate having a gate foot in the first opening, the gate foot having a first width, a gate neck extending from the gate foot and extending for a length over the dielectric passivation layer on both sides of the first opening, the gate neck having a second width wider than the first width of the gate foot, and a gate head extending from the gate neck, the gate head having a third width wider than the second width of the gate neck.