公开(公告)号：US11588482B1

公开(公告)日：2023-02-21

申请号：US17516582

申请日：2021-11-01

Applicant: HRL Laboratories, LLC

Inventor： Chan-Tang Tsen ,  Donald Hitko ,  Susan Morton

IPC: H03K17/687 ,  H03K19/20 ,  H03F3/45

Abstract: A signal processing circuit. In some embodiments, the signal processing circuit includes a first sample and hold circuit and a second sample and hold circuit. The first sample and hold circuit may include: a hold capacitor; an input switch connected between a common input node and the hold capacitor; a signal path amplifier having an input connected to the hold capacitor; and an output switch connected between an output of the signal path amplifier and a common output node. An input of a voltage feedback amplifier may be connected to the hold capacitor, and an output of the voltage feedback amplifier may be operatively coupled to an internal node of the input switch.

公开(公告)号：US11881851B1

公开(公告)日：2024-01-23

申请号：US18155961

申请日：2023-01-18

Applicant: HRL Laboratories, LLC

Inventor： Chan-Tang Tsen ,  Donald Hitko ,  Susan Morton

IPC: H03K17/687 ,  H03K19/20 ,  H03F3/45

CPC classification number: H03K17/6871 ,  H03F3/45475 ,  H03K19/20

Abstract: A signal processing circuit. In some embodiments, the signal processing circuit includes a first sample and hold circuit and a second sample and hold circuit. The first sample and hold circuit may include: a hold capacitor; an input switch connected between a common input node and the hold capacitor; a signal path amplifier having an input connected to the hold capacitor; and an output switch connected between an output of the signal path amplifier and a common output node. An input of a voltage feedback amplifier may be connected to the hold capacitor, and an output of the voltage feedback amplifier may be operatively coupled to an internal node of the input switch.