公开(公告)号：US20230367596A1

公开(公告)日：2023-11-16

申请号：US18314655

申请日：2023-05-09

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Bing Han ,  Yongyu Chen ,  Nan Li ,  Taixu Tian

IPC: G06F9/30

CPC classification number: G06F9/30058

Abstract: An instruction prediction method and apparatus, a system, and a computer-readable storage medium relate to the field of computer technologies. The method includes: a processor obtains a plurality of to-be-executed first IBs, where any first IB includes at least one instruction to be sequentially executed, and the at least one instruction includes one branch instruction; searches, based on branch instructions included in the plurality of first IBs, at least one candidate execution path for a candidate execution path corresponding to the plurality of first IBs, where any candidate execution path indicates a jump relationship between a plurality of second IBs, and a jump relationship indicated by the candidate execution path corresponding to the plurality of first IBs includes a jump relationship between the plurality of first IBs; and predicts, based on the jump relationship between the first IBs, a next instruction corresponding to a branch instruction in each first D3.

公开(公告)号：US20230236727A1

公开(公告)日：2023-07-27

申请号：US18192293

申请日：2023-03-29

Applicant: Huawei Technologies Co., Ltd.

Inventor： Taixu Tian ,  Bing Han

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0653 ,  G06F3/0673

Abstract: This application provides a circuit, a chip, and an electronic device. The circuit includes a first processor and a first processing module connected to the first processor. The first processing module includes a second processor connected to a first memory. A transmission latency generated when the second processor performs read and write operations on the first memory is less than a transmission latency generated when the first processor communicates with the first processing module. Because the transmission latency generated when the second processor performs the read and write operations on the first memory is less than the transmission latency generated when the first processor communicates with the first processing module, a cost of a transmission latency of data in a bus can be reduced.

公开(公告)号：US20130145122A1

公开(公告)日：2013-06-06

申请号：US13763811

申请日：2013-02-11

Applicant: Huawei Technologies Co., Ltd.

Inventor： Gaosong Yin ,  Bing Han

IPC: G06F9/32

CPC classification number: G06F9/32 ,  G06F9/322 ,  G06F9/4486

Abstract: The present invention provides an instruction processing method of a network processor and a network processor. The method includes: when executes a pre-added combined function call instruction, adding an address of its next instruction to a stack top of a first stack; judging, according to the combined function call instruction, whether an enable flag of each additional feature is enabled, and if enabled, adding a function entry address corresponding to an additional feature to the stack top of the first stack; and after finishing judging all enable flags, popping a function entry address in the first stack, and executing a function corresponding to a popped function entry address until the address of the next instruction is popped. In the present invention, only one judgment jump instruction needs to be added to a main line procedure to implement function call of enabled additional features, which saves an instruction execution cycle.

Abstract translation: 本发明提供一种网络处理器和网络处理器的指令处理方法。 该方法包括：当执行预先组合的功能调用指令时，将其下一指令的地址添加到第一堆栈的堆叠顶部; 根据所述组合功能调用指令判断是否启用每个附加特征的使能标志，并且如果启用，则将与附加特征相对应的功能入口地址添加到所述第一堆栈的堆栈顶部; 并且在完成判定所有使能标志之后，弹出第一堆栈中的功能入口地址，并执行与弹出的功能入口地址对应的功能，直到下一条指令的地址被弹出。 在本发明中，仅需要将一条判断跳转指令添加到主线程序中，以实现启用的附加特征的功能调用，从而节省指令执行周期。