公开(公告)号：US20250037749A1

公开(公告)日：2025-01-30

申请号：US18919810

申请日：2024-10-18

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Shihui YIN ,  Weiliang JING ,  Bingwu JI ,  Sitong BU ,  Zhengbo WANG ,  Heng LIAO

IPC: G11C11/22

Abstract: This disclosure relates to a bit line reading circuit, a memory, and an electronic device. An example bit line reading circuit includes a bit line connected to a ferroelectric memory cell. The bit line reading circuit further includes a reference line, a sense amplifier, and a precharge circuit. The sense amplifier and the precharge circuit are separately connected to the bit line and the reference line. The bit line reading circuit further includes a first switch connected to the bit line between the sense amplifier and the precharge circuit, and a second switch connected to the reference line between the sense amplifier and the precharge circuit.

公开(公告)号：US20220406393A1

公开(公告)日：2022-12-22

申请号：US17894233

申请日：2022-08-24

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Bingwu JI ,  Xingyi WANG ,  Yunming ZHOU ,  Tanfu ZHAO ,  Chuhua HU

IPC: G11C29/02 ,  G11C29/52 ,  G11C5/14

Abstract: This application provides a memory, a chip, and a method for storing repair information of the memory. The memory includes a repair circuit that is configured to receive a first signal from a processor and determine to be powered by a first power supply or a second power supply based on a status of the first signal, to store repair information. The repair information is information of the failed bit cells in the memory. The first power supply is zero or in a high impedance state when a system is powered off, and the second power supply is not zero when the system is powered off. The memory further comprises a processing circuit configured to perform communication between the memory and the processor based on the repair information. Therefore, the repair information of the memory can be stored even during power loss.