公开(公告)号：US11245407B2

公开(公告)日：2022-02-08

申请号：US16925657

申请日：2020-07-10

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Dmitry Petrov ,  Ehud Nir

IPC: H03L7/23 ,  H03L7/093 ,  H03L7/089 ,  H03L7/197 ,  H03L7/081

Abstract: The disclosed systems, structures, and methods are directed to a low jitter phase-lock loop (PLL) based frequency synthesizer, comprising a first frequency divider, a phase frequency detector, a charge pump, a low-pass filter, a voltage control oscillator (VCO), a phase interpolator communicatively coupled in a feedback path between the VCO and the phase frequency detector, wherein the phase interpolator comprises a quadrature generator, an input conditioner, a phase rotator, a current mode logic (CML), and a second frequency divider communicatively coupled in the feedback path between the phase interpolator and the phase frequency detector.

公开(公告)号：US12237951B2

公开(公告)日：2025-02-25

申请号：US18349635

申请日：2023-07-10

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Ehud Nir ,  Yanggao Qiu

IPC: H04L25/03 ,  H04L27/00

Abstract: Methods and systems for equalizing signals are disclosed. In an example, a method for equalizing a digital signal at an equalizer, comprises: receiving, at the equalizer, a plurality of samples of the signal in a plurality of unit intervals (UIs) of a channel response of the digital signal, the plurality of samples comprising a first plurality of samples of a primary response and a second plurality of samples of one or more reflection responses; equalizing, by the equalizer, the first plurality of samples using a first set bitwidth; equalizing the second plurality of samples using one or more further set bitwidths, wherein the first set bitwidth is greater than each of the one or more further set bitwidths; and generating, by the equalizer, an equalized digital signal.