METHOD FOR OPTIMIZING FLASH MEMORY CHIP AND RELATED APPARATUS

    公开(公告)号:US20230402121A1

    公开(公告)日:2023-12-14

    申请号:US18455031

    申请日:2023-08-24

    CPC classification number: G11C29/1201 G11C29/12015 G11C29/46

    Abstract: Embodiments of the present disclosure provide a method for optimizing a flash memory chip and a related apparatus. The method comprises, after completing write training of a nonvolatile flash interface (NFI) and establishing a data strobe signal (DQS) trigger point that triggers a memory to identify an electrical level state of a write data signal (DQ) corresponding to the DQS trigger point, determining whether a trigger condition for monitoring the NFI is met, wherein the trigger condition is related to working environmental data of the NFI; upon determining that the trigger condition for monitoring the NFI is met, writing test data to the memory and performing a margin test on the NFI to determine whether the NFI passes a margin test; and upon determining that the NFI does not pass the margin test, initiating interface retraining of the NFI. In this way, the NFI bus channels can be optimized without disk disconnection.

    METHOD AND APPARATUS FOR DETECTING MARGINS OF DATA SIGNAL AND STORAGE DEVICE

    公开(公告)号:US20220276788A1

    公开(公告)日:2022-09-01

    申请号:US17746652

    申请日:2022-05-17

    Abstract: This application provides a method for detecting margins of a data signal. A receive end of a data signal may adjust a voltage of a reference power source; adjust, based on a plurality of reference moments included in a reference moment set, a moment of an edge of a data strobe signal transmitted by a transmit end of the data signal; and during the adjustment, for each reference voltage and each reference moment, determine whether a bit error exists in data obtained by decoding the data signal when the voltage of the reference power source is the reference voltage and the moment of the edge of the data strobe signal is the reference moment, to obtain a timing margin of the data signal at each reference voltage and a voltage margin of the data signal at each reference moment.

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