公开(公告)号：US20220300064A1

公开(公告)日：2022-09-22

申请号：US17834710

申请日：2022-06-07

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Zhongjian CHEN ,  Xiaokun WANG ,  Shibin XU ,  Nianbing LI ,  Liangyi ZHANG

IPC: G06F1/3296

Abstract: This application discloses a voltage scaling method and an electronic device. The method is applied to an electronic device having a processor and a power supply that supplies power to the processor. The method includes the processor sending power supply scaling information to the power supply based on an operating frequency in a next time period. The method further includes the power supply determining, based on the power supply scaling information, a supply voltage Vout used to supply power to the processor. The supply voltage Vout decreases as a load current of the power supply increases. Vmin≤Vout≤V, where Vmin is a lowest supply voltage of the processor at the operating frequency in the next time period, and V is a specified supply voltage of the processor at the operating frequency in the next time period.

公开(公告)号：US20230244617A1

公开(公告)日：2023-08-03

申请号：US18192019

申请日：2023-03-29

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Nianbing LI ,  Yongyao LI ,  Zhongjian CHEN ,  Shibin XU ,  Liangyi ZHANG

IPC: G06F13/16

CPC classification number: G06F13/1689

Abstract: This application provides a memory training method, a memory controller, a processor, and an electronic device. The memory controller keeps transmission delays of N DQs unchanged, adjusts a transmission delay of a DQS, and determines a maximum DQS transmission delay and/or a minimum DQS transmission delay of the DQS when all data carried in the N DQs is correctly transmitted. The memory controller adjusts the transmission delay of the DQS to a target DQS transmission delay between the maximum DQS transmission delay and the minimum DQS transmission delay. The method helps quickly align relative timing positions between the DQS and the N DQs. Therefore, memory training may be repeatedly performed in a working process of the processor, so that the N DQs keep enough timing margins.