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公开(公告)号：US20230237122A1
公开(公告)日：2023-07-27
申请号：US18183394
申请日：2023-03-14
Applicant: HUAWEI TECHNOLOGIES CO., LTD.
Inventor： Wei ZHANG , Tengyi LIN , Xiaoxin XU
Abstract: The present disclosure relates to matrix computing methods, chips, devices, and systems. One example method includes obtaining a computing instruction. The to-be-computed matrix is disassembled to obtain a plurality of disassembled matrices. Precision of a floating point number in the disassembled matrix is lower than precision of a floating point number in the to-be-computed matrix. Computing processing is performed on the plurality of disassembled matrices based on the matrix computing type.
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Patent Agency Ranking
2.发明申请公开(公告)号：US20220350567A1
公开(公告)日：2022-11-03
申请号：US17864732
申请日：2022-07-14
Applicant: HUAWEI TECHNOLOGIES CO., LTD.
Inventor： Qiuping PAN , Tengyi LIN , Shengyu SHEN
Abstract: An arithmetic logic unit comprises multiple (N) adjustment circuits and a multiplier-accumulator. Each of the N adjustment circuits obtains an input floating-point number of a pre-selected input type, and converts the input number to one or more output floating-point numbers of an operation type and precision. The multiplier-accumulator is connected to the N adjustment circuits, and is configured to perform operations on input floating-point numbers of the operation type. The multiplier-accumulator receives a group of floating-point numbers of the operation type from the N adjustment circuits as inputs, performs an operation on the group of floating-point numbers, and generates an operation result floating-point number of the operation type. The multiplier-accumulator then converts the operation result floating-point number to an output floating-point number of a desired type different from the operation type.
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公开(公告)号：US20240184521A1
公开(公告)日：2024-06-06
申请号：US18440254
申请日：2024-02-13
Applicant: HUAWEI TECHNOLOGIES CO., LTD.
Inventor： Tengyi LIN , Kai WANG , Qin WANG
Abstract: The computation apparatus includes a position coordinate comparison circuit and a logical operation circuit. The position coordinate comparison circuit is configured to compare position coordinates of an element value in a first vector with position coordinates of an element value in a second vector, to obtain a coordinate comparison result. The logical operation circuit is configured to compute the first element value and the second element value based on a first comparison result, to obtain a computation value; and output a computation result to a cache. The computation result is related to the computation value. In comparison with a conventional method in which a vector in a compressed format needs to be decompressed first, and then vector computation is performed on a decompressed vector, the computation apparatus can effectively improve efficiency of computing the vector in the compressed format.
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公开(公告)号：US20230196666A1
公开(公告)日：2023-06-22
申请号：US18172353
申请日：2023-02-22
Applicant: HUAWEI TECHNOLOGIES CO., LTD.
Inventor： Tengyi LIN
Abstract: In a three-dimensional shading method, a computing device obtains position information and intensity of at a light source in a target space. The computing device determines, based on the position information and the intensity of the light source, illumination information corresponding to each surface of a three-dimensional object in the target space under illumination of the light source. For each surface, the illumination information corresponding to the surface includes one or more layers of illumination information that reflect illumination information of each position point on the surface under illumination of the light source. The computing device then provides the illumination information of the multiple surfaces of the three-dimensional object to a device that performs shading processing on the target space.
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公开(公告)号：US20230342419A1
公开(公告)日：2023-10-26
申请号：US18343622
申请日：2023-06-28
Applicant: HUAWEI TECHNOLOGIES CO., LTD.
Inventor： Tengyi LIN
Abstract: Example matrix calculation methods and apparatus are described One example method includes calculating, based on vector outer products, a first matrix and a second matrix that are in a compressed format. Vector outer product calculation is performed on a first column vector with reserved row coordinates and a second column vector with reserved column coordinates. Third element values with same position coordinates are accumulated based on indexes of position coordinates to obtain a result matrix.
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6.发明申请公开(公告)号：US20220334798A1
公开(公告)日：2022-10-20
申请号：US17855555
申请日：2022-06-30
Applicant: HUAWEI TECHNOLOGIES CO., LTD.
Inventor： Tengyi LIN , Qiuping Pan , Shengyu Shen , Xiaoxin Xu , Wei Zhang
Abstract: This application discloses a floating-point number multiplication computation method, an apparatus, and an arithmetic logic unit. The method includes: obtaining a plurality of to-be-computed first-precision floating-point numbers; decomposing each to-be-computed first-precision floating-point number to obtain at least two second-precision floating-point numbers, a second precision of the second-precision floating-point number is lower than a first precision of the first-precision floating-point number; determining various combinations including two second-precision floating-point numbers obtained by decomposing different first-precision floating-point numbers; inputting the second-precision floating-point numbers in each combination into a second-precision multiplier to obtain an intermediate computation result corresponding to each combination; and determining a computation result for the plurality of to-be-computed first-precision floating-point numbers based on the intermediate computation result corresponding to each combination.
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