CIRCUIT DESIGN METHOD AND RELATED DEVICE
    1.
    发明公开

    公开(公告)号:US20240135075A1

    公开(公告)日:2024-04-25

    申请号:US18395611

    申请日:2023-12-24

    CPC classification number: G06F30/31

    Abstract: A circuit design method includes: obtaining a first circuit diagram constructed based on a plurality of first components, where each first component includes a first parameter, and the first parameters are parameters that are used in a plurality of processes and that have normalized names; then obtaining indicators of electrical parameters of the plurality of first components based on the first circuit diagram; determining a plurality of second parameters based on the indicators of the electrical parameters of the plurality of first components, where the second parameters are in a one-to-one correspondence with the first parameters; then replacing the first parameters included in the first components with the second parameters, to obtain second components; and outputting a second circuit diagram constructed by the plurality of second components.

    Chip crack detection apparatus
    2.
    发明授权

    公开(公告)号:US11733289B2

    公开(公告)日:2023-08-22

    申请号:US17536545

    申请日:2021-11-29

    CPC classification number: G01R31/2853 G01R31/2894

    Abstract: A chip crack detection apparatus includes a function circuit and a die crack detection module surrounding the function circuit. The die crack detection module includes a front-end-of-line device layer, a laminated structure on the front-end-of-line device layer that includes a conducting wire in the laminated structure, a detection interface, and a capacitor at the front-end-of-line device layer. A first end of the conducting wire is configured to connect to a positive electrode of a power supply. A second end of the conducting wire is configured to connect to a negative electrode of the power supply. The capacitor is connected in parallel between the first end and the second end of the conducting wire. The detection interface is coupled with the conducting wire between the first end and the second end of the conducting wire. The detection interface is configured to detect whether a die crack occurs in the chip.

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