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公开(公告)号：US20190026076A1
公开(公告)日：2019-01-24
申请号：US16039221
申请日：2018-07-18
发明人： Cong Leng , Hao Li , Zesheng Dou , Shenghuo ZHU , Rong JIN
CPC分类号： G06F5/01 , G06F5/08 , G06F7/5443 , G06F7/556 , G06F15/78 , G06F2207/4824 , G06N3/02 , G06N3/063 , G06N3/08
摘要： A method including receiving, by a processor, a computing instruction for a neural network, wherein the computing instruction for the neural network includes a computing rule for the neural network and a connection weight of the neural network, and the connection weight is a power of 2; and inputting, for a multiplication operation in the computing rule for the neural network, a source operand corresponding to the multiplication operation to a shift register, and performing a shift operation based on a connection weight corresponding to the multiplication operation, wherein the shift register outputs a target result operand as a result of the multiplication operation. The neural network uses a shift operation, and a neural network computing speed is increased.
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公开(公告)号：US20180075344A1
公开(公告)日：2018-03-15
申请号：US15675390
申请日：2017-08-11
申请人： SK hynix Inc.
发明人： Kenneth C. MA , Dongwook SUH
CPC分类号： G06N3/04 , G06F7/026 , G06F7/48 , G06F2207/4824 , G06N3/0454 , G06N3/0481 , G06N3/049 , G06N3/06 , G06N3/063 , G06N3/084 , G06N3/088 , G06N5/04 , G11C11/54 , G11C13/0002
摘要： A memory-centric neural network system and operating method thereof includes: a processing unit; semiconductor memory devices coupled to the processing unit, the semiconductor memory devices contain instructions executed by the processing unit; a weight matrix constructed with rows and columns of memory cells, inputs of the memory cells of a same row are connected to one of Axons, outputs of the memory cells of a same column are connected to one of Neurons; timestamp registers registering timestamps of the Axons and the Neurons; and a lookup table containing adjusting values indexed in accordance with the timestamps, the processing unit updates the weight matrix in accordance with the adjusting values.
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公开(公告)号：US20180046916A1
公开(公告)日：2018-02-15
申请号：US15458837
申请日：2017-03-14
申请人： NVIDIA Corporation
发明人： William J. Dally , Angshuman Parashar , Joel Springer Emer , Stephen William Keckler , Larry Robert Dennison
CPC分类号： G06N3/063 , G06F7/523 , G06F7/5443 , G06F2207/4824 , G06N3/04 , G06N3/0454 , G06N3/082 , G06N3/084
摘要： A method, computer program product, and system perform computations using a sparse convolutional neural network accelerator. Compressed-sparse data is received for input to a processing element, wherein the compressed-sparse data encodes non-zero elements and corresponding multi-dimensional positions. The non-zero elements are processed in parallel by the processing element to produce a plurality of result values. The corresponding multi-dimensional positions are processed in parallel by the processing element to produce destination addresses for each result value in the plurality of result values. Each result value is transmitted to a destination accumulator associated with the destination address for the result value.
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公开(公告)号：US20180005108A1
公开(公告)日：2018-01-04
申请号：US15199800
申请日：2016-06-30
CPC分类号： G06N3/063 , G06F7/48 , G06F7/50 , G06F7/523 , G06F2207/4824
摘要： A circuit for emulating the behavior of biological neural circuits, the circuit including a plurality of nodes wherein each node comprises a neuron circuit, a time multiplexed synapse circuit coupled to an input of the neuron circuit, a time multiplexed short term plasticity (STP) circuit coupled to an input of the node and to the synapse circuit, a time multiplexed Spike Timing Dependent Plasticity (STDP) circuit coupled to the input of the node and to the synapse circuit, an output of the node coupled to the neuron circuit; and an interconnect fabric coupled between the plurality of nodes for providing coupling from the output of any node of the plurality of nodes to any input of any other node of the plurality of nodes.
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公开(公告)号：US20170330070A1
公开(公告)日：2017-11-16
申请号：US15445906
申请日：2017-02-28
发明人： Abhronil Sengupta , Sri Harsha Choday , Yusung Kim , Kaushik Roy
CPC分类号： G06N3/0635 , G06F7/48 , G06F7/588 , G06F2207/4824 , G06N3/04 , G06N3/084 , H01L27/228 , H01L27/2409 , H01L43/06 , H01L43/08
摘要： An electronic neuron device that includes a thresholding unit which utilizes current-induced spin-orbit torque (SOT). A two-step switching scheme is implemented with the device. In the first step, a charge current through heavy metal (HM) places the magnetization of a nano-magnet along the hard-axis (i.e. an unstable point for the magnet). In the second step, the device receives a current (from an electronic synapse) which moves the magnetization from the unstable point to one of the two stable states. The polarity of the net synaptic current determines the final orientation of the magnetization. A resistive crossbar array may also be provided which functions as the synapse generating a bipolar current that is a weighted sum of the inputs of the device.
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公开(公告)号：US20180359084A1
公开(公告)日：2018-12-13
申请号：US15620034
申请日：2017-06-12
IPC分类号： H04L9/08
CPC分类号： H04L9/08 , G06F7/483 , G06F21/602 , G06F2207/4824 , G06N20/00 , H04L9/008 , H04L9/0816 , H04L9/0838 , H04L9/0894
摘要： Systems, methods, and computer-executable instructions for secure data analysis using encrypted data. An encryption key and a decryption key are created. The security of encryption using the encryption key and the decryption key are based upon factoring. A computation key is created based upon the encryption key. Data is encrypted using the encryption key. The encrypted data and the computation key are provided to a remote system. The remote system is requested to perform data analysis on the encrypted data. An encrypted result of the data analysis is received from the remote system. The encrypted result of the data analysis is decrypted with the decryption key.
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公开(公告)号：US20180330239A1
公开(公告)日：2018-11-15
申请号：US16041160
申请日：2018-07-20
发明人： Tianshi CHEN , Shaoli LIU , Qi GUO , Yunji CHEN
CPC分类号： G06N3/084 , G06F7/4876 , G06F2207/4824 , G06N3/063
摘要： A compression coding apparatus for artificial neural network, including memory interface unit, instruction cache, controller unit and computing unit, wherein the computing unit is configured to perform corresponding operation to data from the memory interface unit according to instructions of controller unit; the computing unit mainly performs three steps operation: step one is to multiply input neuron by weight data; step two is to perform adder tree computing and add the weighted output neuron obtained in step one level-by-level via adder tree, or add bias to output neuron to get biased output neuron; step three is to perform activation function operation to get final output neuron. The present disclosure also provides a method for compression coding of multi-layer neural network.
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8.发明申请公开(公告)号：US20180322958A1
公开(公告)日：2018-11-08
申请号：US15966454
申请日：2018-04-30
申请人： Efthymios Kalafatis
发明人： Efthymios Kalafatis
CPC分类号： G16H50/70 , G06F7/08 , G06F16/24578 , G06F16/2465 , G06F2207/4824 , G06N3/006 , G06N3/08 , G06N5/003 , G06N5/041 , G06N20/00 , G06N20/10 , G06N20/20
摘要： Techniques are disclosed for discovering, biological elements, functions and pathways, and environmental and nutritional factors related to diseases and medical syndromes. The techniques preprocess database query results and harmonize data using natural language processing before transforming them into the frequency space. The transformed results are analyzed with various categories of machine learning algorithms whose results are normalized, ranked and selectively combined, weighted or un-weighted, to produce a single result ranking the most important elements affecting a target disease or medical syndrome. The invention also uses alternative algorithms producing hypotheses on associations between medical topics, which are used as suggestions for exploratory medical research
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公开(公告)号：US20180307975A1
公开(公告)日：2018-10-25
申请号：US15855604
申请日：2017-12-27
申请人： Intel Corporation
发明人： Kevin Nealis , Randy Huang
CPC分类号： G06N3/063 , G06F7/523 , G06F7/5443 , G06F2207/3828 , G06F2207/4824 , G06N3/08
摘要： Systems and methods are related to improving throughput of neural networks in integrated circuits by combining values in operands to increase compute density. A system includes an integrated circuit (IC) having multiplier circuitry. The IC receives a first value and a second value in a first operand. The IC performs a multiplication operation, via the multiplier circuitry, on the first operand and a second operand to produce a first multiplied product based at least in part on the first value and a second multiplied product based at least in part on the second value.
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公开(公告)号：US20180260710A1
公开(公告)日：2018-09-13
申请号：US15975075
申请日：2018-05-09
发明人： Shijin Zhang , Qi Guo , Yunji Chen , Tianshi Chen
CPC分类号： G06N3/082 , G06F7/5443 , G06F9/30145 , G06F17/15 , G06F17/16 , G06F2207/4824 , G06K9/6256 , G06N3/0454 , G06N3/0481 , G06N3/063
摘要： Aspects for modifying data in a multi-layer neural network (MNN) acceleration processor for neural networks are described herein. As an example, the aspects may include receiving a predetermined weight value array and connection data. Further, the aspects may include modifying the weight values included in the predetermined weight value array based on the connection data. Further still, the aspects may include calculating one or more groups of output data based on the modified weight values.
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