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公开(公告)号:US20220383951A1
公开(公告)日:2022-12-01
申请号:US17873186
申请日:2022-07-26
Inventor: Xingsheng WANG , Fan Yang , Lingjun Zhou , Chengxu WANG , Xiangshui MIAO
IPC: G11C13/00
Abstract: A read and write circuit of a three-dimensional phase-change memory including an operation control circuit and a read and write operation circuit connected to each other. The operation control circuit is configured to load a correct operation pulse onto the read and write operation circuit. A read and write unit in the read and write operation circuit is connected to a memory cell and is configured to load the correct operation pulse onto the memory cell corresponding to the three-dimensional phase-change memory and to mirror the correct operation pulse to a mirror current. A bandgap reference source and a hysteresis comparator are connected to a mirror circuit branch. A feedback chopper circuit loop is connected across the memory cell and the mirror circuit branch and is configured to monitor a current flowing through the memory cell in real time.
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公开(公告)号:US20240371438A1
公开(公告)日:2024-11-07
申请号:US18031356
申请日:2022-07-07
Inventor: Xingsheng WANG , Yinghao MA , Fan Yang , Chengxu WANG , Menghua HUANG , Xiangshui MIAO
IPC: G11C13/00
Abstract: A high-speed and large-current adjustable pulse circuit, an operating circuit and an operating method of a phase-change memory are provided. The high-speed and large-current adjustable pulse circuit is provided with a clamping structure, a current mirror structure and a leakage current shutdown structure. The clamping structure including a clamping operational amplifier and a first MOS transistor is configured to generate a reference current. The current mirror structure is configured to generate an output current proportional to the reference current. The leakage current shutdown structure is configured to turn off the current mirror structure and reduce leakage current when pulse disappear. In this way, a device with an adjustable current and a reduced leakage current is realized.
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