公开(公告)号：US20210407589A1

公开(公告)日：2021-12-30

申请号：US17049024

申请日：2019-11-17

Applicant: Huazhong University of Science and Technology

Inventor： Xingsheng WANG ,  Enming HUANG ,  Xiangshui MIAO

IPC: G11C13/00 ,  G11C7/06

Abstract: A read-write circuit mainly includes a read circuit and a write circuit. The write circuit comprises: a first voltage selector and a first voltage follower circuit that is electrically connected to the memristor storage array. The read-write circuit further includes a second voltage selector and a second voltage follower circuit that is electrically connected to the memristor storage array. Voltage stable following during bipolar writing is selected through the foregoing selector. Meanwhile, the reading circuit is provided with a variable resistor to select an access mode. The actual read-out voltage and the output voltage passing through the reference resistor under the same read voltage are input into a differential amplifier to obtain read-out data.

公开(公告)号：US20240371438A1

公开(公告)日：2024-11-07

申请号：US18031356

申请日：2022-07-07

Applicant: HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGY

Inventor： Xingsheng WANG ,  Yinghao MA ,  Fan Yang ,  Chengxu WANG ,  Menghua HUANG ,  Xiangshui MIAO

IPC: G11C13/00

Abstract: A high-speed and large-current adjustable pulse circuit, an operating circuit and an operating method of a phase-change memory are provided. The high-speed and large-current adjustable pulse circuit is provided with a clamping structure, a current mirror structure and a leakage current shutdown structure. The clamping structure including a clamping operational amplifier and a first MOS transistor is configured to generate a reference current. The current mirror structure is configured to generate an output current proportional to the reference current. The leakage current shutdown structure is configured to turn off the current mirror structure and reduce leakage current when pulse disappear. In this way, a device with an adjustable current and a reduced leakage current is realized.

公开(公告)号：US20230170908A1

公开(公告)日：2023-06-01

申请号：US17794620

申请日：2021-07-05

Applicant: HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGY

Inventor： Xingsheng WANG ,  Yujie SONG ,  Qiwen WU ,  Xiangshui MIAO

IPC: H03K19/1776 ,  G11C13/00

CPC classification number: H03K19/1776 ,  G11C13/004 ,  G11C13/0069 ,  H03K19/21

Abstract: A non-volatile Boolean logic circuit based on memristors and an operation method, which performs logic operations on the input logic value P and/or the input logic value Q. The logic circuit includes: a controller, a memristor M1, a memristor M2 and a resistor. The controller sets the memristor M2 to a high resistance state before performing the logic operation. When performing the logic operation, a voltage A is applied to the memristor M1, a voltage B is applied to the memristor M2, a voltage C is applied to the resistor. The resistance state of the memristor M2 is the result of the logic operation. When a logic operation is performed on the logic value P and the logic value Q or only on the logic value Q, the controller further sets the memristor M1 to the resistance state corresponding to the logic value Q before performing the logic operation.

公开(公告)号：US20220383951A1

公开(公告)日：2022-12-01

申请号：US17873186

申请日：2022-07-26

Applicant: HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGY

Inventor： Xingsheng WANG ,  Fan Yang ,  Lingjun Zhou ,  Chengxu WANG ,  Xiangshui MIAO

IPC: G11C13/00

Abstract: A read and write circuit of a three-dimensional phase-change memory including an operation control circuit and a read and write operation circuit connected to each other. The operation control circuit is configured to load a correct operation pulse onto the read and write operation circuit. A read and write unit in the read and write operation circuit is connected to a memory cell and is configured to load the correct operation pulse onto the memory cell corresponding to the three-dimensional phase-change memory and to mirror the correct operation pulse to a mirror current. A bandgap reference source and a hysteresis comparator are connected to a mirror circuit branch. A feedback chopper circuit loop is connected across the memory cell and the mirror circuit branch and is configured to monitor a current flowing through the memory cell in real time.