公开(公告)号：US20130162292A1

公开(公告)日：2013-06-27

申请号：US13333229

申请日：2011-12-21

申请人： Hadi Parandeh Afshar ,  David Novo Bruña ,  Paolo Ienne Lopez

发明人： Hadi Parandeh Afshar ,  David Novo Bruña ,  Paolo Ienne Lopez

IPC分类号： H03K19/20 ,  H03K19/173

CPC分类号： H03K19/1737 ,  H03K19/17728

摘要： New logic blocks capable of replacing the use of Look-Up Tables (LUTs) in integrated circuits, such as Field-Programmable Gate Arrays (FPGAs), are disclosed herein. In one embodiment, the new logic block is an AND-Inverter Cone (AIC), which is a binary tree including one or more AND gates with a programmable conditional inversion and a number of intermediary outputs. Compared to LUTs, AICs are richer in terms of input and output bandwidth, because the area of the AICs grows only linearly with the number of inputs. Also, the delay grows only logarithmically with the input count. The new logic blocks can map circuits more efficiently than LUTs, because the AICs are multi-output blocks and can cover more logic depth due to the higher input bandwidth.

摘要翻译： 本文公开了能够替代集成电路中的查找表（LUT）的使用的新逻辑块，例如现场可编程门阵列（FPGA）。 在一个实施例中，新的逻辑块是AND-Inverter Cone（AIC），它是一个二进制树，它包括一个或多个具有可编程条件反转和多个中间输出的与门。 与LUT相比，AIC在输入和输出带宽方面更加丰富，因为AIC的面积仅随着输入数量的增加而呈线性增长。 此外，延迟仅与输入计数对数地增长。 新的逻辑块可以比LUT更有效地映射电路，因为AIC是多输出块，并且由于较高的输入带宽可以覆盖更多的逻辑深度。

公开(公告)号：US08836368B2

公开(公告)日：2014-09-16

申请号：US13333229

申请日：2011-12-21

申请人： Hadi Parandeh Afshar ,  David Novo Bruña ,  Paolo Ienne Lopez

发明人： Hadi Parandeh Afshar ,  David Novo Bruña ,  Paolo Ienne Lopez

IPC分类号： H03K19/20 ,  H03K19/173

CPC分类号： H03K19/1737 ,  H03K19/17728

摘要： New logic blocks capable of replacing the use of Look-Up Tables (LUTs) in integrated circuits, such as Field-Programmable Gate Arrays (FPGAs), are disclosed herein. In one embodiment, the new logic block is an AND-Inverter Cone (AIC), which is a binary tree including one or more AND gates with a programmable conditional inversion and a number of intermediary outputs. Compared to LUTs, AICs are richer in terms of input and output bandwidth, because the area of the AICs grows only linearly with the number of inputs. Also, the delay grows only logarithmically with the input count. The new logic blocks can map circuits more efficiently than LUTs, because the AICs are multi-output blocks and can cover more logic depth due to the higher input bandwidth.

摘要翻译： 本文公开了能够替代集成电路中的查找表（LUT）的使用的新逻辑块，例如现场可编程门阵列（FPGA）。 在一个实施例中，新的逻辑块是AND-Inverter Cone（AIC），它是一个二进制树，它包括一个或多个具有可编程条件反转和多个中间输出的与门。 与LUT相比，AIC在输入和输出带宽方面更加丰富，因为AIC的面积仅随着输入数量的增加而呈线性增长。 此外，延迟仅与输入计数对数地增长。 新的逻辑块可以比LUT更有效地映射电路，因为AIC是多输出块，并且由于较高的输入带宽可以覆盖更多的逻辑深度。