公开(公告)号：US08225017B1

公开(公告)日：2012-07-17

申请号：US12251367

申请日：2008-10-14

申请人： Haiming Tang ,  Yu-Tang Hsieh

发明人： Haiming Tang ,  Yu-Tang Hsieh

IPC分类号： G06F13/38 ,  H04J3/02

CPC分类号： H03M9/00 ,  G01R31/31709 ,  H04L25/03343

摘要： A high-speed SerDes transmitter which may reduce power supply introduced data dependent jitter. Instead of trying to make the output voltage of a power supply of a pre-driver constant, the output voltage of the power supply is returned to its normal level periodically, e.g., after each bit time to follow the data rate of an input data stream. A complementary pre-driver may be used to create a complementary data stream which may be at the same data rate as the input data rate. The complementary data stream may have a transition when there is no transition between two consecutive bits in the input data stream, but have no transition when there is a transition in the input data stream. As a result, there is a transition at the power supply during each bit time, and the power supply may be drawn back to its normal level during each bit time. Consequently, the power supply variation is periodic at the beat of the input data rate, and the power supply may have the same impact on each data bit. Thus, each bit in the input data stream may see the same level of power supply, and data dependent jitter may be reduced or eliminated.

摘要翻译： 可以减少电源的高速SerDes发射器引入数据相关的抖动。 代替尝试使预驱动器的电源的输出电压恒定，电源的输出电压周期性地返回到其正常电平，例如，在每个比特时间之后，跟随输入数据流的数据速率 。 可以使用互补的预驱动器来创建可以与输入数据速率相同的数据速率的互补数据流。 当输入数据流中的两个连续位之间没有转换时，互补数据流可以具有转换，但是当在输入数据流中存在转换时，互补数据流可能没有转换。 结果，在每个位时间期间，在电源处存在转换，并且在每个位时间期间电源可以被恢复到其正常电平。 因此，电源变化在输入数据速率的节拍处是周期性的，并且电源可能对每个数据位具有相同的影响。 因此，输入数据流中的每个位可以看到相同的电源电平，并且可以减少或消除数据相关的抖动。

公开(公告)号：US06777994B2

公开(公告)日：2004-08-17

申请号：US10271553

申请日：2002-10-17

申请人： Ju-Ming Chou ,  Yu-Tang Hsieh ,  Jieh-Tsorng Wu

发明人： Ju-Ming Chou ,  Yu-Tang Hsieh ,  Jieh-Tsorng Wu

IPC分类号： H03H1126

CPC分类号： H03K3/0322 ,  G06F1/04 ,  H03K5/133 ,  H03K2005/00208

摘要： To reduce the effect of the phase shift error originated from the mismatch of the delay units of the clock generator, we propose to add one more set of averaging amplifiers and averaging impedances, such as resistors, into the circuit of the clock generator. In the clock generator, outputs of all delay units connect to inputs of all averaging amplifiers respectively, and the averaging impedances connect the corresponding outputs of two adjacent averaging amplifiers, so as to form a closed loop. When a phase shift error occurs in the delay units, the averaging current through the averaging impedances will decrease the phase shift error in each stage. Specifically, the output impedance of the averaging amplifiers approaches infinite, and thus the resistance of the averaging impedances is relatively small. Therefore almost all signal currents will go through the averaging impedances, and an optimal averaging effect is achieved. In addition, we apply the simple voltage-mode phase interpolation technique to the averaging impedances for better phase resolution and more output phases. Further, utilizing the folding architecture, our proposed clock generator can output high-frequency clock signals at low-frequency operating clock.

摘要翻译： 为了减少源自时钟发生器的延迟单元不匹配的相移误差的影响，我们建议在时钟发生器的电路中增加一组平均放大器和平均阻抗（如电阻）。 在时钟发生器中，所有延迟单元的输出分别连接到所有平均放大器的输入，平均阻抗连接两个相邻平均放大器的相应输出，以形成闭环。 当在延迟单元中出现相移误差时，通过平均阻抗的平均电流将降低每个阶段的相移误差。 具体地，平均放大器的输出阻抗接近无穷大，因此平均阻抗的电阻相对较小。 因此，几乎所有的信号电流将经过平均阻抗，并且实现了最佳的平均效应。 此外，我们将简单的电压模式相位插值技术应用于平均阻抗，以获得更好的相位分辨率和更多的输出相位。 此外，利用折叠架构，我们提出的时钟发生器可以在低频工作时钟输出高频时钟信号。