公开(公告)号：US4851891A

公开(公告)日：1989-07-25

申请号：US154104

申请日：1988-02-09

申请人： Hajime Kubosawa ,  Mitsugu Naitoh

发明人： Hajime Kubosawa ,  Mitsugu Naitoh

IPC分类号： H03K19/177 ,  H01L23/535 ,  H01L27/118

CPC分类号： H01L27/11807 ,  H01L23/535 ,  H01L2924/0002 ,  Y10S257/923

摘要： A gate array comprises a semiconductor substrate, a plurality of mutually parallel basic cell columns each made up of a plurality of basic cells formed on the semiconductor substrate, where each of the basic cells comprise a pair of first p-channel transistor and first n-channel transistor, a plurality of interconnection regions each formed between two mutually adjacent ones of the basic cell columns, and specific cells buried in one or a plurality of predetermined ones of the interconnection regions, where each of the specific cells comprise at least a second p-channel transistor and a second n-channel transistor which constitute a transmission gate.

公开(公告)号：US5047976A

公开(公告)日：1991-09-10

申请号：US658467

申请日：1991-02-22

申请人： Gensuke Goto ,  Hajime Kubosawa

发明人： Gensuke Goto ,  Hajime Kubosawa

IPC分类号： G06F7/50 ,  G06F7/507

CPC分类号： G06F7/507

摘要： An operation circuit for M-bits parallel full addition includes partitioned adders and first and second multiplexers. Each of the first multiplexers selects one of paired provisional carry signals C.sub.ns-1 (1) and C.sub.ns-1 (0) supplied from the s-th partitioned adder, depending on the value of the real carry signal C.sub.(s-1)n-1 supplied from the (s-1)th partitioned adder, the selected one of the provisional carry signals being the real carry signal C.sub.ns-1 to be progatatd from the s-th partitioned adder. Each of the second multiplexers generates a pair of provisional carry signals Ck*(1) and Ck*(0) (k=n(s+1)-1, n(s+2) -1, . . . , n(s+l)-1) by referring to paired provisional carry signals Cr(1) (or Cr*(1); r=k-n=ns-1) and Cr(0) (or Cr*(0); k-n=ns-1) which are lower by n digits than the ones to be generated. Then the second multiplexers generate l real carry signals Ck at the same time by selecting either the provisional carry signal Ck*(1) or Ck*(0), depending on the real carry signal C.sub.(s-1)n-1 relating to a digit which is one digit lower than the lowest-order digit of the s-th partitioned adder.

摘要翻译： 用于M位并行全加法的操作电路包括分区加法器和第一和第二多路复用器。 每个第一多路复用器根据实际进位信号C（s-1）n的值选择从第s分区加法器提供的配对临时进位信号Cns-1（1）和Cns-1（0） -1，从第（s-1）个分频加法器提供，所选择的一个临时进位信号是从第s个分频加法器进行的实际进位信号Cns-1。 每个第二多路复用器产生一对临时进位信号Ck *（1）和Ck *（0）（k = n（s + 1）-1，n（s + 2）-1，...，n（ 通过参考成对临时进位信号Cr（1）（或Cr *（1）; r = kn = ns-1）和Cr（0）（或Cr *（0）; kn = ns -1），它们比要生成的数字低n位。 然后，第二复用器根据与实际进位信号Ck（1）相关的实际进位信号C（s-1）n-1同时选择临时进位信号Ck *（1）或Ck *（0） 比第s分区加法器的最低位数字低一位的数字。

公开(公告)号：US5682521A

公开(公告)日：1997-10-28

申请号：US272939

申请日：1994-07-11

申请人： Hajime Kubosawa

发明人： Hajime Kubosawa

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3885 ,  G06F9/3836

摘要： A microprocessor which can simultaneously execute a plurality of instructions (predetermined number of instructions, i.e., m-instructions which are transferred to a plurality of registers. When the instructions within the m-instructions are transferred to the registers, the instructions are executed in order of the executable state of the instructions regardless of order of the transfer. Further, when n-instructions (n>m) are simultaneously set to the executable state for every one clock cycle, the n-instructions are executed in order of the transfer of the instructions. Accordingly, it is possible to realize high speed and effective execution of instructions.

摘要翻译： 可以同时执行多个指令（预定数量的指令，即传送到多个寄存器的m指令）的微处理器，当m指令内的指令被传送到寄存器时，指令按顺序执行 指令的可执行状态，而不管转移顺序如何，另外，当n个指令（n> m）每一个时钟周期同时被设置为可执行状态时，以指令的顺序执行n个指令 因此，可以实现指令的高速且有效的执行。

公开(公告)号：US5434810A

公开(公告)日：1995-07-18

申请号：US883247

申请日：1992-05-07

申请人： Gensuke Goto ,  Hajime Kubosawa

发明人： Gensuke Goto ,  Hajime Kubosawa

IPC分类号： G06F7/50 ,  G06F7/508

CPC分类号： G06F7/508 ,  G06F2207/4812

摘要： A binary operator comprises a plurality of carry select adder circuits each including a cumulative carry propagate signal generating means and a cumulative carry generate signal generating means and/or a plurality of block look ahead carry generator circuits each including a cumulative block carry propagate signal and cumulative block carry generate signal generating means and a real carry signal generating means. The carry select adder circuit does not simultaneously generate two presumed sum signals and select and output one of the presumed sum signals, but directly performs operations on a carry propagate signal, a cumulative carry propagate signal and a cumulative carry generate signal which are necessary for generating the presumed sum signal pair and a real carry signal to calculate the real sum signal. The block look ahead carry generator circuit does not simultaneously generate two presumed carry signals and select and output one of the presumed carry signals, but uses a cumulative block carry propagate signal, a cumulative block carry generate signal and a carry signal to directly generate the real carry signal. The number of elements of the binary operator is greatly reduced without sacrificing the high speed of computation since two presumed sum or carry signals are never generated in parallel.

摘要翻译： 二进制运算器包括多个进位选择加法器电路，每个进位选择加法器电路各自包括累积进位传播信号产生装置和累积进位产生信号产生装置和/或多个前进块传送发生器电路，每个包括累积块携带传播信号和累积 块携带产生信号发生装置和实际进位信号发生装置。 进位选择加法器电路不同时产生两个推定的和信号，并选择并输出一个预测的和信号，而是直接执行对于产生所需的进位传播信号，累积进位传播信号和累积进位产生信号的操作 假设和信号对和实际进位信号来计算实和信号。 块前进进位发生器电路不同时产生两个假设的进位信号，并选择并输出其中一个假设的进位信号，而是使用累积块进位传播信号，累积块进位生成信号和进位信号直接产生真实的 进位信号。 二进制运算符的元素的数量大大减少，而不牺牲计算的高速度，因为两个假定的和或进位信号不会并行地产生。

公开(公告)号：US4837461A

公开(公告)日：1989-06-06

申请号：US155571

申请日：1988-02-12

申请人： Hajime Kubosawa ,  Masato Ishiguro

发明人： Hajime Kubosawa ,  Masato Ishiguro

IPC分类号： H01L21/82 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/04 ,  H01L27/092 ,  H01L27/118

CPC分类号： H01L27/11807

摘要： A master slice type integrated circuit in which various circuits may be formed by varying the routing of interconnections, comprises a plurality of input/output cells being arranged in a peripheral region on a semiconductor chip; a plurality of basic cell columns each comprising a plurality of basic cells arranged in a predetermined direction, each basic cell constituting transistors; an interconnection region formed on the chip, for accommodating a data bus; and a plurality of latch cells being arranged in the basic cell columns, for keeping a potential of a data bus laid on the interconnection region to prevent the data bus from being changed into a floating state, each latch cell comprising transistors, each of which has a driving capability smaller than that of each transistor of the basic cell.