公开(公告)号：US4851891A

公开(公告)日：1989-07-25

申请号：US154104

申请日：1988-02-09

申请人： Hajime Kubosawa ,  Mitsugu Naitoh

发明人： Hajime Kubosawa ,  Mitsugu Naitoh

IPC分类号： H03K19/177 ,  H01L23/535 ,  H01L27/118

CPC分类号： H01L27/11807 ,  H01L23/535 ,  H01L2924/0002 ,  Y10S257/923

摘要： A gate array comprises a semiconductor substrate, a plurality of mutually parallel basic cell columns each made up of a plurality of basic cells formed on the semiconductor substrate, where each of the basic cells comprise a pair of first p-channel transistor and first n-channel transistor, a plurality of interconnection regions each formed between two mutually adjacent ones of the basic cell columns, and specific cells buried in one or a plurality of predetermined ones of the interconnection regions, where each of the specific cells comprise at least a second p-channel transistor and a second n-channel transistor which constitute a transmission gate.

公开(公告)号：US4701919A

公开(公告)日：1987-10-20

申请号：US810143

申请日：1985-12-18

申请人： Mitsugu Naitoh ,  Yoshiyuki Suehiro

发明人： Mitsugu Naitoh ,  Yoshiyuki Suehiro

IPC分类号： G06F11/22 ,  G01R31/28 ,  G06F15/78 ,  G11C11/401 ,  G11C29/10 ,  G11C29/12 ,  G11C29/46

CPC分类号： G11C29/46

摘要： In a semiconductor device comprising a memory cell array and a test pattern generating circuit, the test pattern generating circuit generates the test pattern and transmits the test pattern to the memory cell array when receiving the least significant bit signal of address signals supplied to the memory cell array and the control signal.

摘要翻译： 在包括存储单元阵列和测试图形生成电路的半导体器件中，测试图形产生电路产生测试图形，并且当接收到提供给存储单元的地址信号的最低有效位信号时，将测试图案发送到存储单元阵列 阵列和控制信号。

公开(公告)号：US5040150A

公开(公告)日：1991-08-13

申请号：US527977

申请日：1990-05-24

申请人： Mitsugu Naitoh ,  Junichi Shikatani

发明人： Mitsugu Naitoh ,  Junichi Shikatani

IPC分类号： G01R31/3185 ,  G11C29/12

CPC分类号： G11C29/12 ,  G01R31/318505 ,  G11C11/16

摘要： A semiconductor integrated circuit device comprising a first circuit forming a random logic and outputting a plurality of first parallel data of plural bits, a second circuit which receives the plurality of first parallel data and supplies a plurality of second parallel data of plural bits to the first circuit, and a test circuit which divides a part of external parallel data of plural bits smaller in number than the first parallel data into a plurality of third parallel data of plural bits in such a manner that the plurality of third parallel data correspond in number to the plurality of first parallel data.