公开(公告)号：US20060050574A1

公开(公告)日：2006-03-09

申请号：US11259703

申请日：2005-10-26

申请人： Harald Streif ,  Stefan Wuensche ,  Mike Killian

发明人： Harald Streif ,  Stefan Wuensche ,  Mike Killian

IPC分类号： G11C7/00

CPC分类号： G11C7/1021 ,  G11C11/4076 ,  G11C2207/002 ,  G11C2207/2281 ,  G11C2207/229

摘要： A memory device (10) includes an array (12) of memory cells arranged in rows and columns. Preferably, each memory cell includes a pass transistor coupled to a storage capacitor. A row decoder (18) is coupled to rows of memory cells while a column decoder (14) is coupled to columns of the memory cells. The column decoder (14) includes an enable input. A variable delay (32) has an output coupled to the enable input of the column decoder (14). The variable delay (32) receives an indication (R/W′) of whether a current cycle is a read cycle or a write cycle. In the preferred embodiment, a signal provided at the output of the variable delay (32) is delayed if the current cycle is a read cycle compared to if the current cycle is a write cycle.

摘要翻译： 存储器件（10）包括以行和列布置的存储单元阵列（12）。 优选地，每个存储单元包括耦合到存储电容器的传输晶体管。 行解码器（18）耦合到行存储器单元，而列解码器（14）耦合到存储器单元的列。 列解码器（14）包括使能输入。 可变延迟（32）具有耦合到列解码器（14）的使能输入的输出。 可变延迟（32）接收当前周期是读周期还是写周期的指示（R / W'）。 在优选实施例中，如果当前周期是写周期，则当前周期是读周期时，在可变延迟（32）的输出处提供的信号被延迟。

公开(公告)号：US07149134B2

公开(公告)日：2006-12-12

申请号：US11259703

申请日：2005-10-26

申请人： Harald Streif ,  Stefan Wuensche ,  Mike Killian

发明人： Harald Streif ,  Stefan Wuensche ,  Mike Killian

IPC分类号： G11C7/00

CPC分类号： G11C7/1021 ,  G11C11/4076 ,  G11C2207/002 ,  G11C2207/2281 ,  G11C2207/229

摘要： A memory device (10) includes an array (12) of memory cells arranged in rows and columns. Preferably, each memory cell includes a pass transistor coupled to a storage capacitor. A row decoder (18) is coupled to rows of memory cells while a column decoder (14) is coupled to columns of the memory cells. The column decoder (14) includes an enable input. A variable delay (32) has an output coupled to the enable input of the column decoder (14). The variable delay (32) receives an indication (R/W′) of whether a current cycle is a read cycle or a write cycle. In the preferred embodiment, a signal provided at the output of the variable delay (32) is delayed if the current cycle is a read cycle compared to if the current cycle is a write cycle.

公开(公告)号：US07035150B2

公开(公告)日：2006-04-25

申请号：US10285027

申请日：2002-10-31

申请人： Harald Streif ,  Stefan Wuensche ,  Mike Killian

发明人： Harald Streif ,  Stefan Wuensche ,  Mike Killian

IPC分类号： G11C7/00

CPC分类号： G11C7/1021 ,  G11C11/4076 ,  G11C2207/002 ,  G11C2207/2281 ,  G11C2207/229

摘要： A memory device (10) includes an array (12) of memory cells arranged in rows and columns. Preferably, each memory cell includes a pass transistor coupled to a storage capacitor. A row decoder is coupled to rows of memory cells while a column decoder (14) is coupled to columns of the memory cells. The column decoder (14) includes an enable input. A variable delay (32) has an output coupled to the enable input of the column decoder (14). The variable delay (32) receives an indication (R/W′) of whether a current cycle is a read cycle or a write cycle. In the preferred embodiment, a signal provided at the output of the variable delay (32) is delayed if the current cycle is a read cycle compared to if the current cycle is a write cycle.

摘要翻译： 存储器件（10）包括以行和列布置的存储单元阵列（12）。 优选地，每个存储单元包括耦合到存储电容器的传输晶体管。 行解码器耦合到行存储器单元，而列解码器（14）耦合到存储器单元的列。 列解码器（14）包括使能输入。 可变延迟（32）具有耦合到列解码器（14）的使能输入的输出。 可变延迟（32）接收当前周期是读周期还是写周期的指示（R / W'）。 在优选实施例中，如果当前周期是写周期，则当前周期是读周期时，在可变延迟（32）的输出处提供的信号被延迟。