公开(公告)号：US20080168331A1

公开(公告)日：2008-07-10

申请号：US11650169

申请日：2007-01-05

申请人： Thomas Vogelsang ,  Harald Streif ,  Pete Chlumecky ,  Josef Schnell

发明人： Thomas Vogelsang ,  Harald Streif ,  Pete Chlumecky ,  Josef Schnell

IPC分类号： G11C29/00 ,  G06F11/07

CPC分类号： G11C7/1006 ,  G06F11/1044 ,  G11C2029/0411

摘要： A memory includes an array of memory cells and an error correction code circuit. The error correction code circuit is configured to receive a first portion of a first data word from an external circuit and a second portion of the first data word from the array of memory cells, combine the first portion and the second portion to provide the first data word, and encode the first data word for writing to the array of memory cells.

摘要翻译： 存储器包括存储器单元阵列和纠错码电路。 误差校正码电路被配置为从存储器单元阵列的外部电路和第一数据字的第二部分接收第一数据字的第一部分，组合第一部分和第二部分以提供第一数据 字，并对第一数据字进行编码以写入存储器单元阵列。

公开(公告)号：US20070147153A1

公开(公告)日：2007-06-28

申请号：US11313650

申请日：2005-12-22

申请人： Helmut Schneider ,  Harald Streif

发明人： Helmut Schneider ,  Harald Streif

IPC分类号： G11C5/14 ,  G11C7/00

CPC分类号： G11C8/08 ,  G11C5/147 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4085 ,  G11C29/783 ,  G11C2211/4067 ,  G11C2211/4068

摘要： A semiconductor integrated circuit device and method for reducing gate induced leakage current associated with circuits of the semiconductor electrical device, such as a semiconductor integrated circuit memory device. During a standby mode, a voltage supplied to a plurality of circuits is reduced so as to reduce gate induced leakage (GIDL) current associated with said plurality of circuits. During time intervals while in the standby mode, the voltage supplied to a subset of said plurality of circuits is increased to a level necessary for a refresh function associated with said subset of said plurality of circuits and then it is reduced upon completion of said refresh function. In the example a semiconductor memory device, the circuits that are manipulated in this manner are wordline driver circuits. A cyclical self-refresh operation is provided to refresh the WLs associated with subsets of the wordline driver circuits to reduce the overall GIDL current associated with the plurality of wordline driver circuits.

摘要翻译： 一种半导体集成电路器件和方法，用于减少与诸如半导体集成电路存储器件的半导体电子器件的电路相关联的栅极感应漏电流。 在待机模式期间，提供给多个电路的电压减小，以便减少与所述多个电路相关联的栅极感应泄漏（GIDL）电流。 在处于待机模式的时间间隔期间，提供给所述多个电路的子集的电压增加到与所述多个电路的所述子集相关联的刷新功能所需的电平，然后在所述刷新功能完成时减小 。 在该示例中，半导体存储器件，以这种方式操作的电路是字线驱动器电路。 提供循环自刷新操作以刷新与字线驱动器电路的子集相关联的WL，以减少与多个字线驱动器电路相关联的总体GIDL电流。

公开(公告)号：US20080142854A1

公开(公告)日：2008-06-19

申请号：US11611222

申请日：2006-12-15

申请人： Harald Streif

发明人： Harald Streif

IPC分类号： H01L29/76 ,  H01L21/8248 ,  G05F1/10

CPC分类号： G11C11/4085

摘要： An electrical circuit comprising a first metal oxide silicon (MOS) n type field effect transistor (NFET) or p type field effect transistor (PFET) and a second MOS NFET or PFET of the same conductivity type as the first NFET or PFET, wherein the drain of the first NFET or PFET is directly connected to the source of the second NFET or PFET, and wherein the gate of the second NFET or PFET is at a voltage value which is equal to or lower than the drain voltage value of the second NFET or PFET in the case of an NFET and equal to or higher than the drain voltage value of the second NFET or PFET in the case of a PFET.

摘要翻译： 一种包括第一金属氧化物硅（MOS）n型场效应晶体管（NFET）或p型场效应晶体管（PFET）以及与第一NFET或PFET相同导电类型的第二MOS NFET或PFET的电路，其中， 第一NFET或PFET的漏极直接连接到第二NFET或PFET的源极，并且其中第二NFET或PFET的栅极处于等于或低于第二NFET或PFET的漏极电压值的电压值 或者在NFET的情况下为PFET，并且在PFET的情况下等于或高于第二NFET或PFET的漏极电压值。

公开(公告)号：US07149134B2

公开(公告)日：2006-12-12

申请号：US11259703

申请日：2005-10-26

申请人： Harald Streif ,  Stefan Wuensche ,  Mike Killian

发明人： Harald Streif ,  Stefan Wuensche ,  Mike Killian

IPC分类号： G11C7/00

CPC分类号： G11C7/1021 ,  G11C11/4076 ,  G11C2207/002 ,  G11C2207/2281 ,  G11C2207/229

摘要： A memory device (10) includes an array (12) of memory cells arranged in rows and columns. Preferably, each memory cell includes a pass transistor coupled to a storage capacitor. A row decoder (18) is coupled to rows of memory cells while a column decoder (14) is coupled to columns of the memory cells. The column decoder (14) includes an enable input. A variable delay (32) has an output coupled to the enable input of the column decoder (14). The variable delay (32) receives an indication (R/W′) of whether a current cycle is a read cycle or a write cycle. In the preferred embodiment, a signal provided at the output of the variable delay (32) is delayed if the current cycle is a read cycle compared to if the current cycle is a write cycle.

公开(公告)号：US06956409B2

公开(公告)日：2005-10-18

申请号：US10651281

申请日：2003-08-28

申请人： Harald Streif ,  Oliver Kiehl ,  Mike Killian

发明人： Harald Streif ,  Oliver Kiehl ,  Mike Killian

IPC分类号： H03K5/1252 ,  H03K17/22 ,  H03K5/153

CPC分类号： H03K17/223 ,  H03K5/1252

摘要： System and method for detecting a reference signal. A preferred embodiment comprises a latch (such as the latch 320) and a filter (such as the filter 325). The latch tracks a reference signal at its input and reflects the reference signal at its output. The filter can be coupled to the output of the latch and may inject a delay to help eliminate the effects of glitches and noise. When the reference signal reaches a specified value, a control signal from the filter causes the latch to store the reference signal. A delay imparted by the filter ensures that the latch does not store the reference signal until a finite amount of time after the reference signal reaches the specified value.

摘要翻译： 用于检测参考信号的系统和方法。 优选实施例包括闩锁（例如闩锁320）和过滤器（例如过滤器325）。 锁存器在其输入端跟踪参考信号，并在其输出端反映参考信号。 滤波器可以耦合到锁存器的输出，并且可以注入延迟以帮助消除毛刺和噪声的影响。 当参考信号达到指定值时，来自滤波器的控制信号使闩锁存储参考信号。 由滤波器赋予的延迟确保了锁存器不存储参考信号，直到参考信号达到指定值之后的有限量的时间。

公开(公告)号：US20080137470A1

公开(公告)日：2008-06-12

申请号：US11635164

申请日：2006-12-07

申请人： Josef Schnell ,  Farrukh Aquil ,  Harald Streif

发明人： Josef Schnell ,  Farrukh Aquil ,  Harald Streif

IPC分类号： G11C8/00

CPC分类号： G11C5/025 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C11/4076

摘要： One embodiment provides a memory device including a memory bank, a first receiver, and a second receiver. The memory bank includes memory cells. The first receiver is configured to receive a clock signal and provide a data clock signal based on the clock signal. The second receiver is configured to receive the clock signal and provide a command/address clock signal based on the clock signal. The first receiver provides the data clock signal to output read data from the memory cells. The second receiver provides the command/address clock signal to execute commands.

摘要翻译： 一个实施例提供了一种包括存储体，第一接收器和第二接收器的存储器件。 存储体包括存储单元。 第一接收器被配置为接收时钟信号并且基于时钟信号提供数据时钟信号。 第二接收器被配置为接收时钟信号并且基于时钟信号提供命令/地址时钟信号。 第一个接收器提供数据时钟信号以从存储器单元输出读取数据。 第二个接收器提供命令/地址时钟信号来执行命令。

公开(公告)号：US07359271B2

公开(公告)日：2008-04-15

申请号：US11313650

申请日：2005-12-22

申请人： Helmut Schneider ,  Harald Streif

发明人： Helmut Schneider ,  Harald Streif

IPC分类号： G11C7/00

CPC分类号： G11C8/08 ,  G11C5/147 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4085 ,  G11C29/783 ,  G11C2211/4067 ,  G11C2211/4068

摘要： A semiconductor integrated circuit device and method for reducing gate induced leakage current associated with circuits of the semiconductor electrical device, such as a semiconductor integrated circuit memory device. During a standby mode, a voltage supplied to a plurality of circuits is reduced so as to reduce gate induced leakage (GIDL) current associated with said plurality of circuits. During time intervals while in the standby mode, the voltage supplied to a subset of said plurality of circuits is increased to a level necessary for a refresh function associated with said subset of said plurality of circuits and then it is reduced upon completion of said refresh function. In the example a semiconductor memory device, the circuits that are manipulated in this manner are wordline driver circuits. A cyclical self-refresh operation is provided to refresh the WLs associated with subsets of the wordline driver circuits to reduce the overall GIDL current associated with the plurality of wordline driver circuits.

摘要翻译： 一种半导体集成电路器件和方法，用于减少与诸如半导体集成电路存储器件的半导体电子器件的电路相关联的栅极感应漏电流。 在待机模式期间，提供给多个电路的电压减小，以便减少与所述多个电路相关联的栅极感应泄漏（GIDL）电流。 在处于待机模式的时间间隔期间，提供给所述多个电路的子集的电压增加到与所述多个电路的所述子集相关联的刷新功能所需的电平，然后在所述刷新功能完成时减小 。 在该示例中，半导体存储器件，以这种方式操作的电路是字线驱动器电路。 提供循环自刷新操作以刷新与字线驱动器电路的子集相关联的WL，以减少与多个字线驱动器电路相关联的总体GIDL电流。

公开(公告)号：US20060050574A1

公开(公告)日：2006-03-09

申请号：US11259703

申请日：2005-10-26

申请人： Harald Streif ,  Stefan Wuensche ,  Mike Killian

发明人： Harald Streif ,  Stefan Wuensche ,  Mike Killian

IPC分类号： G11C7/00

CPC分类号： G11C7/1021 ,  G11C11/4076 ,  G11C2207/002 ,  G11C2207/2281 ,  G11C2207/229

摘要： A memory device (10) includes an array (12) of memory cells arranged in rows and columns. Preferably, each memory cell includes a pass transistor coupled to a storage capacitor. A row decoder (18) is coupled to rows of memory cells while a column decoder (14) is coupled to columns of the memory cells. The column decoder (14) includes an enable input. A variable delay (32) has an output coupled to the enable input of the column decoder (14). The variable delay (32) receives an indication (R/W′) of whether a current cycle is a read cycle or a write cycle. In the preferred embodiment, a signal provided at the output of the variable delay (32) is delayed if the current cycle is a read cycle compared to if the current cycle is a write cycle.

摘要翻译： 存储器件（10）包括以行和列布置的存储单元阵列（12）。 优选地，每个存储单元包括耦合到存储电容器的传输晶体管。 行解码器（18）耦合到行存储器单元，而列解码器（14）耦合到存储器单元的列。 列解码器（14）包括使能输入。 可变延迟（32）具有耦合到列解码器（14）的使能输入的输出。 可变延迟（32）接收当前周期是读周期还是写周期的指示（R / W'）。 在优选实施例中，如果当前周期是写周期，则当前周期是读周期时，在可变延迟（32）的输出处提供的信号被延迟。

公开(公告)号：US06724676B1

公开(公告)日：2004-04-20

申请号：US10299037

申请日：2002-11-18

申请人： Ronny Schneider ,  Harald Streif

发明人： Ronny Schneider ,  Harald Streif

IPC分类号： G11C700

CPC分类号： H03K3/0375 ,  G11C5/005 ,  G11C7/1045 ,  G11C17/18

摘要： Embodiments of the present invention generally provide a soft error-resistant latch circuit. The latch circuit generally includes first and second inverters, each formed by at least two transistors. At least one delay element decouples the gate of at least one of the transistors of one of the inverters from a diffusion area of at least one of the transistors of the other inverter.

摘要翻译： 本发明的实施例通常提供一种软错误锁存电路。 锁存电路通常包括由至少两个晶体管形成的第一和第二反相器。 至少一个延迟元件将一个反相器的至少一个晶体管的栅极与另一个反相器的至少一个晶体管的扩散区域去耦。

公开(公告)号：US07840876B2

公开(公告)日：2010-11-23

申请号：US11676774

申请日：2007-02-20

申请人： Andre Sturm ,  Harald Streif

发明人： Andre Sturm ,  Harald Streif

IPC分类号： G11C29/00

CPC分类号： G11C7/1006 ,  G06F11/1052 ,  G11C8/08 ,  G11C8/12 ,  G11C8/14 ,  G11C11/4096

摘要： The present invention includes a memory device with a data memory and an error correction code control circuit. The data memory stores data parity information for error correction. The error correction code control circuit is configured to receive a selection signal indicative of whether an error correction mode is to be used. Power to access the portion of the memory storing the parity information is disabled when the error correction mode is enabled.

摘要翻译： 本发明包括具有数据存储器和纠错码控制电路的存储器件。 数据存储器存储用于纠错的数据奇偶校验信息。 纠错码控制电路被配置为接收指示是否使用纠错模式的选择信号。 当启用纠错模式时，禁用访问存储奇偶校验信息的存储部分的电源。