公开(公告)号：US07060529B2

公开(公告)日：2006-06-13

申请号：US10841162

申请日：2004-05-07

申请人： Manfred Reithinger ,  Mike Killian ,  Gerd Frankowsky ,  Oliver Kiehl ,  Gerhard Mueller ,  Ernst Stahl ,  Hartmud Terletzki ,  Thomas Vogelsang

发明人： Manfred Reithinger ,  Mike Killian ,  Gerd Frankowsky ,  Oliver Kiehl ,  Gerhard Mueller ,  Ernst Stahl ,  Hartmud Terletzki ,  Thomas Vogelsang

IPC分类号： H01L21/50 ,  H01L21/30

CPC分类号： H01L25/18 ,  H01L23/50 ,  H01L23/5382 ,  H01L27/105 ,  H01L27/10894 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor packaging arrangement, or module, includes a printed circuit board having an electrical interconnect thereon and a semiconductor package mounted to the printed circuit board. The semiconductor package includes a fractional portion of a semiconductor wafer having a plurality of integrated circuit chips thereon, such chips being separated by regions in the fractional portion of the wafer. The fractional portion of the wafer has a plurality of electrical contacts electrically connected to the chips. The package also includes a dielectric member having an electrical conductor thereon. The electrical conductor are electrically connected to the plurality of electrical contacts of the plurality of chips to electrically interconnect such plurality of chips with portions of the electrical conductor spanning the regions in the fractional portion of the wafer. A connector is provided for electrically connecting the electrical conductor of the package to the electrical interconnect of the printed circuit board.

摘要翻译： 半导体封装装置或模块包括其上具有电互连的印刷电路板和安装到印刷电路板的半导体封装。 半导体封装包括其上具有多个集成电路芯片的半导体晶片的分数部分，这些芯片由晶片的分数部分中的区域分隔开。 晶片的分数部分具有电连接到芯片的多个电触点。 封装还包括其上具有电导体的电介质构件。 电导体电连接到多个芯片的多个电触头，以将这些多个芯片与跨越晶片的分数部分中的区域的电导体的部分电互连。 提供一种用于将封装的电导体电连接到印刷电路板的电互连的连接器。

公开(公告)号：US20050001298A1

公开(公告)日：2005-01-06

申请号：US10841162

申请日：2004-05-07

申请人： Manfred Reithinger ,  Mike Killian ,  Gerd Frankowsky ,  Oliver Kiehl ,  Gerhard Mueller ,  Ernst Stahl ,  Hartmud Terletzki ,  Thomas Vogelsang

发明人： Manfred Reithinger ,  Mike Killian ,  Gerd Frankowsky ,  Oliver Kiehl ,  Gerhard Mueller ,  Ernst Stahl ,  Hartmud Terletzki ,  Thomas Vogelsang

IPC分类号： H01L21/8242 ,  H01L23/50 ,  H01L23/538 ,  H01L25/18 ,  H01L27/105 ,  H01L23/544

CPC分类号： H01L25/18 ,  H01L23/50 ,  H01L23/5382 ,  H01L27/105 ,  H01L27/10894 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor packaging arrangement, or module, includes a printed circuit board having an electrical interconnect thereon and a semiconductor package mounted to the printed circuit board. The semiconductor package includes a fractional portion of a semiconductor wafer having a plurality of integrated circuit chips thereon, such chips being separated by regions in the fractional portion of the wafer. The fractional portion of the wafer has a plurality of electrical contacts electrically connected to the chips. The package also includes a dielectric member having an electrical conductor thereon. The electrical conductor are electrically connected to the plurality of electrical contacts of the plurality of chips to electrically interconnect such plurality of chips with portions of the electrical conductor spanning the regions in the fractional portion of the wafer. A connector is provided for electrically connecting the electrical conductor of the package to the electrical interconnect of the printed circuit board.

摘要翻译： 半导体封装装置或模块包括其上具有电互连的印刷电路板和安装到印刷电路板的半导体封装。 半导体封装包括其上具有多个集成电路芯片的半导体晶片的分数部分，这些芯片由晶片的分数部分中的区域分隔开。 晶片的分数部分具有电连接到芯片的多个电触点。 封装还包括其上具有电导体的电介质构件。 电导体电连接到多个芯片的多个电触头，以将这些多个芯片与跨越晶片的分数部分中的区域的电导体的部分电互连。 提供一种用于将封装的电导体电连接到印刷电路板的电互连的连接器。

公开(公告)号：US06815803B1

公开(公告)日：2004-11-09

申请号：US09596129

申请日：2000-06-16

申请人： Manfred Reithinger ,  Mike Killian ,  Gerd Frankowsky ,  Oliver Kiehl ,  Gerhard Mueller ,  Ernst Stahl ,  Hartmud Terletzki ,  Thomas Vogelsang

发明人： Manfred Reithinger ,  Mike Killian ,  Gerd Frankowsky ,  Oliver Kiehl ,  Gerhard Mueller ,  Ernst Stahl ,  Hartmud Terletzki ,  Thomas Vogelsang

IPC分类号： H01L23544

CPC分类号： H01L25/18 ,  H01L23/50 ,  H01L23/5382 ,  H01L27/105 ,  H01L27/10894 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor packaging arrangement, or module, includes a printed circuit board having an electrical interconnect thereon and a semiconductor package mounted to the printed circuit board. The semiconductor package includes a fractional portion of a semiconductor wafer having a plurality of integrated circuit chips thereon, such chips being separated by regions in the fractional portion of the wafer. The fractional portion of the wafer has a plurality of electrical contacts electrically connected to the chips. The package also includes a dielectric member having an electrical conductor thereon. The electrical conductor are electrically connected to the plurality of electrical contacts of the plurality of chips to electrically interconnect such plurality of chips with portions of the electrical conductor spanning the regions in the fractional portion of the wafer. A connector is provided for electrically connecting the electrical conductor of the package to the electrical interconnect of the printed circuit board.

摘要翻译： 半导体封装装置或模块包括其上具有电互连的印刷电路板和安装到印刷电路板的半导体封装。 半导体封装包括其上具有多个集成电路芯片的半导体晶片的分数部分，这些芯片由晶片的分数部分中的区域分隔开。 晶片的分数部分具有电连接到芯片的多个电触点。 封装还包括其上具有电导体的电介质构件。 电导体电连接到多个芯片的多个电触头，以将这些多个芯片与跨越晶片的分数部分中的区域的电导体的部分电互连。 提供一种用于将封装的电导体电连接到印刷电路板的电互连的连接器。

公开(公告)号：US07035150B2

公开(公告)日：2006-04-25

申请号：US10285027

申请日：2002-10-31

申请人： Harald Streif ,  Stefan Wuensche ,  Mike Killian

发明人： Harald Streif ,  Stefan Wuensche ,  Mike Killian

IPC分类号： G11C7/00

CPC分类号： G11C7/1021 ,  G11C11/4076 ,  G11C2207/002 ,  G11C2207/2281 ,  G11C2207/229

摘要： A memory device (10) includes an array (12) of memory cells arranged in rows and columns. Preferably, each memory cell includes a pass transistor coupled to a storage capacitor. A row decoder is coupled to rows of memory cells while a column decoder (14) is coupled to columns of the memory cells. The column decoder (14) includes an enable input. A variable delay (32) has an output coupled to the enable input of the column decoder (14). The variable delay (32) receives an indication (R/W′) of whether a current cycle is a read cycle or a write cycle. In the preferred embodiment, a signal provided at the output of the variable delay (32) is delayed if the current cycle is a read cycle compared to if the current cycle is a write cycle.

摘要翻译： 存储器件（10）包括以行和列布置的存储单元阵列（12）。 优选地，每个存储单元包括耦合到存储电容器的传输晶体管。 行解码器耦合到行存储器单元，而列解码器（14）耦合到存储器单元的列。 列解码器（14）包括使能输入。 可变延迟（32）具有耦合到列解码器（14）的使能输入的输出。 可变延迟（32）接收当前周期是读周期还是写周期的指示（R / W'）。 在优选实施例中，如果当前周期是写周期，则当前周期是读周期时，在可变延迟（32）的输出处提供的信号被延迟。

公开(公告)号：US20050046451A1

公开(公告)日：2005-03-03

申请号：US10651281

申请日：2003-08-28

申请人： Harald Streif ,  Oliver Kiehl ,  Mike Killian

发明人： Harald Streif ,  Oliver Kiehl ,  Mike Killian

IPC分类号： H03K5/1252 ,  H03K17/22 ,  H03L7/00

CPC分类号： H03K17/223 ,  H03K5/1252

摘要： System and method for detecting a reference signal. A preferred embodiment comprises a latch (such as the latch 320) and a filter (such as the filter 325). The latch tracks a reference signal at its input and reflects the reference signal at its output. The filter can be coupled to the output of the latch and may inject a delay to help eliminate the effects of glitches and noise. When the reference signal reaches a specified value, a control signal from the filter causes the latch to store the reference signal. A delay imparted by the filter ensures that the latch does not store the reference signal until a finite amount of time after the reference signal reaches the specified value.

摘要翻译： 用于检测参考信号的系统和方法。 优选实施例包括闩锁（例如闩锁320）和过滤器（例如过滤器325）。 锁存器在其输入端跟踪参考信号，并在其输出端反映参考信号。 滤波器可以耦合到锁存器的输出，并且可以注入延迟以帮助消除毛刺和噪声的影响。 当参考信号达到指定值时，来自滤波器的控制信号使闩锁存储参考信号。 由滤波器赋予的延迟确保了锁存器不存储参考信号，直到参考信号达到指定值之后的有限量的时间。

公开(公告)号：US5995436A

公开(公告)日：1999-11-30

申请号：US187153

申请日：1998-11-06

申请人： Martin Brox ,  Franz Freimuth ,  Mike Killian ,  Naokazu Miyawaki ,  Thilo Schaffroth

发明人： Martin Brox ,  Franz Freimuth ,  Mike Killian ,  Naokazu Miyawaki ,  Thilo Schaffroth

IPC分类号： G11C11/41 ,  G11C5/14 ,  G11C7/20 ,  G11C7/22 ,  G11C11/401

CPC分类号： G11C7/22 ,  G11C5/143 ,  G11C7/20

摘要： A circuit embodying the invention includes a gating circuit responsive to a first control signal and to a second externally supplied control signal having an active state and an inactive state. The first control signal is produced by a power supply circuit which is responsive to the application of an externally supplied operating voltage for producing an "internal" operating voltage and which produces the first control signal having an active state when the internal operating voltage reaches a predetermined value. The gating circuit has an output for producing a third control signal which is enabling only if the second control signal goes from its inactive state to its active state when the first control signal is already in, and remains in, its active state. The gating circuit prevents a chip from operating in an unintended mode at power-up.

摘要翻译： 体现本发明的电路包括响应于第一控制信号的门控电路和具有活动状态和非活动状态的第二外部提供的控制信号。 第一控制信号由电源电路产生，电源电路响应于施加外部提供的工作电压以产生“内部”工作电压，并且当内部工作电压达到预定的工作电压时产生具有有效状态的第一控制信号 值。 门控电路具有用于产生第三控制信号的输出，该第三控制信号仅在第一控制信号已经处于其活动状态时才能使第二控制信号从其无效状态变为其活动状态。 门控电路可防止芯片在上电时以非预期模式运行。

公开(公告)号：US20060050574A1

公开(公告)日：2006-03-09

申请号：US11259703

申请日：2005-10-26

申请人： Harald Streif ,  Stefan Wuensche ,  Mike Killian

发明人： Harald Streif ,  Stefan Wuensche ,  Mike Killian

IPC分类号： G11C7/00

CPC分类号： G11C7/1021 ,  G11C11/4076 ,  G11C2207/002 ,  G11C2207/2281 ,  G11C2207/229

摘要： A memory device (10) includes an array (12) of memory cells arranged in rows and columns. Preferably, each memory cell includes a pass transistor coupled to a storage capacitor. A row decoder (18) is coupled to rows of memory cells while a column decoder (14) is coupled to columns of the memory cells. The column decoder (14) includes an enable input. A variable delay (32) has an output coupled to the enable input of the column decoder (14). The variable delay (32) receives an indication (R/W′) of whether a current cycle is a read cycle or a write cycle. In the preferred embodiment, a signal provided at the output of the variable delay (32) is delayed if the current cycle is a read cycle compared to if the current cycle is a write cycle.

摘要翻译： 存储器件（10）包括以行和列布置的存储单元阵列（12）。 优选地，每个存储单元包括耦合到存储电容器的传输晶体管。 行解码器（18）耦合到行存储器单元，而列解码器（14）耦合到存储器单元的列。 列解码器（14）包括使能输入。 可变延迟（32）具有耦合到列解码器（14）的使能输入的输出。 可变延迟（32）接收当前周期是读周期还是写周期的指示（R / W'）。 在优选实施例中，如果当前周期是写周期，则当前周期是读周期时，在可变延迟（32）的输出处提供的信号被延迟。

公开(公告)号：US06730989B1

公开(公告)日：2004-05-04

申请号：US09596130

申请日：2000-06-16

申请人： Manfred Reithinger ,  Mike Killian ,  Gerd Frankowsky ,  Oliver Kiehl ,  Gerhard Mueller ,  Ernst Stahl ,  Hartmud Terletzki ,  Thomas Vogelsang

发明人： Manfred Reithinger ,  Mike Killian ,  Gerd Frankowsky ,  Oliver Kiehl ,  Gerhard Mueller ,  Ernst Stahl ,  Hartmud Terletzki ,  Thomas Vogelsang

IPC分类号： H01L23544

CPC分类号： H01L23/5382 ,  H01L23/50 ,  H01L25/18 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor packaging arrangement, or module, includes a printed circuit board having an electrical interconnect thereon and a semiconductor package mounted to the printed circuit board. The semiconductor package includes a fractional portion of a semiconductor wafer having a plurality of integrated circuit chips thereon, such chips being separated by regions in the fractional portion of the wafer. The fractional portion of the wafer has a plurality of electrical contacts electrically connected to the chips. The package also includes a dielectric member having an electrical conductor thereon. The electrical conductor are electrically connected to the plurality of electrical contacts of the plurality of chips to electrically interconnect such plurality of chips with portions of the electrical conductor spanning the regions in the fractional portion of the wafer. A connector is provided for electrically connecting the electrical conductor of the package to the electrical interconnect of the printed circuit board.

摘要翻译： 半导体封装装置或模块包括其上具有电互连的印刷电路板和安装到印刷电路板的半导体封装。 半导体封装包括其上具有多个集成电路芯片的半导体晶片的分数部分，这些芯片由晶片的分数部分中的区域分隔开。 晶片的分数部分具有电连接到芯片的多个电触点。 封装还包括其上具有电导体的电介质构件。 电导体电连接到多个芯片的多个电触头，以将这些多个芯片与跨越晶片的分数部分中的区域的电导体的部分电互连。 提供一种用于将封装的电导体电连接到印刷电路板的电互连的连接器。

公开(公告)号：US07149134B2

公开(公告)日：2006-12-12

申请号：US11259703

申请日：2005-10-26

申请人： Harald Streif ,  Stefan Wuensche ,  Mike Killian

发明人： Harald Streif ,  Stefan Wuensche ,  Mike Killian

IPC分类号： G11C7/00

CPC分类号： G11C7/1021 ,  G11C11/4076 ,  G11C2207/002 ,  G11C2207/2281 ,  G11C2207/229

摘要： A memory device (10) includes an array (12) of memory cells arranged in rows and columns. Preferably, each memory cell includes a pass transistor coupled to a storage capacitor. A row decoder (18) is coupled to rows of memory cells while a column decoder (14) is coupled to columns of the memory cells. The column decoder (14) includes an enable input. A variable delay (32) has an output coupled to the enable input of the column decoder (14). The variable delay (32) receives an indication (R/W′) of whether a current cycle is a read cycle or a write cycle. In the preferred embodiment, a signal provided at the output of the variable delay (32) is delayed if the current cycle is a read cycle compared to if the current cycle is a write cycle.

公开(公告)号：US06956409B2

公开(公告)日：2005-10-18

申请号：US10651281

申请日：2003-08-28

申请人： Harald Streif ,  Oliver Kiehl ,  Mike Killian

发明人： Harald Streif ,  Oliver Kiehl ,  Mike Killian

IPC分类号： H03K5/1252 ,  H03K17/22 ,  H03K5/153

CPC分类号： H03K17/223 ,  H03K5/1252

摘要： System and method for detecting a reference signal. A preferred embodiment comprises a latch (such as the latch 320) and a filter (such as the filter 325). The latch tracks a reference signal at its input and reflects the reference signal at its output. The filter can be coupled to the output of the latch and may inject a delay to help eliminate the effects of glitches and noise. When the reference signal reaches a specified value, a control signal from the filter causes the latch to store the reference signal. A delay imparted by the filter ensures that the latch does not store the reference signal until a finite amount of time after the reference signal reaches the specified value.

摘要翻译： 用于检测参考信号的系统和方法。 优选实施例包括闩锁（例如闩锁320）和过滤器（例如过滤器325）。 锁存器在其输入端跟踪参考信号，并在其输出端反映参考信号。 滤波器可以耦合到锁存器的输出，并且可以注入延迟以帮助消除毛刺和噪声的影响。 当参考信号达到指定值时，来自滤波器的控制信号使闩锁存储参考信号。 由滤波器赋予的延迟确保了锁存器不存储参考信号，直到参考信号达到指定值之后的有限量的时间。