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公开(公告)号：US07055118B1
公开(公告)日：2006-05-30
申请号：US10790650
申请日：2004-03-01
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A method and apparatus for improved formal scan chain equivalence checking to verify the operation of components in a VLSI integrated circuit is described in connection with using symbolic simulation for verification of scan chain equivalency between different modeling representations of a circuit-under-test. The present invention enhances previous techniques by loading each scannable state-element in the circuit design with a symbolic expression that characterizes the logical location of the element and performing a scan shift operation to verify the contents of each scannable state-element at the scan-out and other primary output pins of the design.
摘要翻译： 结合使用符号仿真来验证被测电路的不同建模表示之间的扫描链等效性，描述了用于改进的形式扫描链等效性检查以验证VLSI集成电路中的组件的操作的方法和装置。 本发明通过在电路设计中加载表征元件的逻辑位置的符号表达来执行扫描移位操作来验证扫描出的每个可扫描状态元件的内容来增强先前的技术， 和其他主要输出引脚的设计。
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2.发明授权公开(公告)号：US06466590B1
公开(公告)日：2002-10-15
申请号：US09439572
申请日：1999-11-12
申请人： Chang-Jin Park , Jae-Hun Jeong
发明人： Chang-Jin Park , Jae-Hun Jeong
IPC分类号： H04J304
CPC分类号： H04L12/5601 , H04L49/108 , H04L49/258 , H04L49/309 , H04L2012/5681
摘要： The present invention is related to a device and method for processing a cell group in a common memory switch, in which output ports in the common memory switch are divided into an individualized output port group associated with only one output port and a grouped output port group associated with a plurality of output ports, wherein each output port is assigned to a unique group number.
摘要翻译： 本发明涉及一种用于处理公共存储器交换机中的小区组的设备和方法，其中公共存储器交换机中的输出端口被划分为仅与一个输出端口相关联的个性化输出端口组和分组的输出端口组 与多个输出端口相关联，其中每个输出端口被分配给唯一的组号。
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