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公开(公告)号：US5623198A
公开(公告)日：1997-04-22
申请号：US576465
申请日：1995-12-21
申请人： Harold L. Massie , G. Mark Johnston
发明人： Harold L. Massie , G. Mark Johnston
CPC分类号： G05F1/575
摘要： A switching regulator circuit comprises a drive circuit, a switching transistor, an output stage and a pre-drive circuit that are coupled in series. The pre-drive circuit is coupled to the drive circuit to apply a pre-drive signal which varies the duty cycle and frequency of a series of drive pulses which activate and deactivate the switching transistor thereby adjusting a voltage of the switching regulator circuit. The pre-drive circuit utilizes a comparator in combination with a hysteresis network to vary the oscillation frequency of the pre-drive signal.
摘要翻译： 开关调节器电路包括串联耦合的驱动电路，开关晶体管，输出级和预驱动电路。 预驱动电路耦合到驱动电路以施加预驱动信号，该预驱动信号改变驱动和去激活开关晶体管的一系列驱动脉冲的占空比和频率，从而调节开关调节器电路的电压。 预驱动电路利用与迟滞网络组合的比较器来改变预驱动信号的振荡频率。
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公开(公告)号：US5777461A
公开(公告)日：1998-07-07
申请号：US799385
申请日：1996-12-31
申请人： Harold L. Massie , G. Mark Johnston
发明人： Harold L. Massie , G. Mark Johnston
CPC分类号： H02M1/38 , H02M3/1588 , H02M3/33561 , Y02B70/1466
摘要： A DC-DC voltage conversion provides a voltage to a processor in a mobile computer system using a high side power FET and a low side power FET, each having a variable gate discharge time dependent on the applied battery voltage. The power FETs are arranged in a synchronous totem pole configuration with a junction point therebetween, coupled between a voltage input terminal and ground, with the junction point coupled to a voltage output terminal. Each of the power FETs is driven by a FET driver, with the driver being coupled to the output of a comparator comparing a reference voltage with the output voltage. To avoid cross-conduction, the high side power FET and the low side power FET are coupled to each other in such a manner that the event of one turning off will turn on the other after a dead time determined by the threshold sense circuit, plus delays of the devices used in the embodiment.
摘要翻译： DC-DC电压转换使用高边功率FET和低边功率FET向移动计算机系统中的处理器提供电压，每个具有取决于施加的电池电压的可变栅极放电时间。 功率FET被布置成同步图腾柱配置，其间具有连接点，耦合在电压输入端子和地之间，其中结点耦合到电压输出端子。 每个功率FET由FET驱动器驱动，驱动器耦合到比较参考电压与输出电压的比较器的输出。 为了避免交叉导通，高边功率FET和低边功率FET以这样的方式彼此耦合，使得在由阈值感测电路确定的死区时间之后，一次关断的事件将在另一个之后导通，另外 在实施例中使用的装置的延迟。
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