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1.发明授权公开(公告)号：US07721134B2
公开(公告)日：2010-05-18
申请号：US11566576
申请日：2006-12-04
CPC分类号： G01R31/3171 , B82Y25/00 , G01R33/093
摘要： A method and system for determining the eye pattern margin parameters of a receiver system during diagnostic testing is presented. The circuitry in the receiver's front end comprises a series of latches, XOR gates and OR gates which first provide the data samples and edge samples, i.e., data sampled at the rising or falling edge of an (edge) clock characterized by a phase delay relative to the data sampling clock. The receiver also comprises optimization circuitry for the ideal alignment of the edge clock (edges) with the data edges. The method further provides for a phase shifting of the edge clock to the left and right from the ideal/locked position to screen the data eye pattern in order to compute the Bit Error Rate (BER) value. The position of the edge clock relative to the data sampling clock determines the horizontal eye opening for the computed BER.
摘要翻译： 提出了一种用于在诊断测试期间确定接收机系统的眼图边缘参数的方法和系统。 接收机前端的电路包括一系列锁存器，XOR门和OR门，它们首先提供数据样本和边缘采样，即在（边沿）时钟的上升沿或下降沿采样的数据，其特征在于相位延迟相对 到数据采样时钟。 接收机还包括用于边缘时钟（边缘）与数据边缘的理想对准的优化电路。 该方法还提供了边缘时钟从理想/锁定位置向左和向右移相以屏蔽数据眼图，以便计算误码率（BER）值。 边缘时钟相对于数据采样时钟的位置决定了计算的BER的水平眼睛开度。
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公开(公告)号：US07916820B2
公开(公告)日：2011-03-29
申请号：US11608962
申请日：2006-12-11
IPC分类号： H04L7/00
CPC分类号： H04L7/0004 , H04L7/0334
摘要： A dual mode clock and data recovery (CDR) system is disclosed. A fast locking, oversampling CDR acquisition module can begin the process to quickly create a data acquisition clock signal in start up data acquisition conditions. When at least some data can be extracted from the incoming data stream, the CDR system can indicate such stability and switch to accept control from a low power CDR maintenance module. The low power CDR maintenance module can then fine tune and maintain the timing of the data acquisition signal. If the quality of the data lock under CDR maintenance module control degrades to a sufficient degree, the high power CDR acquisition module can be re-enables and re-assert control from the low power module until such time as the lock quality is again sufficient for the low power module to be used.
摘要翻译： 公开了一种双模式时钟和数据恢复（CDR）系统。 快速锁定，过采样CDR采集模块可以开始该过程，以在启动数据采集条件下快速创建数据采集时钟信号。 当从输入数据流中至少提取一些数据时，CDR系统可以指示这种稳定性，并切换到接受来自低功率CDR维护模块的控制。 低功率CDR维护模块可以微调并保持数据采集信号的定时。 如果CDR维护模块控制下的数据锁定质量下降到足够的程度，高功率CDR采集模块可以重新启用并重新从低功率模块重新进行控制，直到锁定质量再次足够 要使用的低功耗模块。
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公开(公告)号：US07983368B2
公开(公告)日：2011-07-19
申请号：US11608948
申请日：2006-12-11
IPC分类号： H04L7/00
CPC分类号： H04L7/042 , H04L7/0004 , H04L7/0334
摘要： A sampling clock signal controller for receivers of digital data is disclosed. Specific bit patterns of a data waveform can be identified, and stored time samples of the waveform that correspond to the specific bit patterns can be analyzed to improve the timing of a sampling clock signal. These “time-amplitude” samples on known bit patterns can be utilized to determine if a sample on the data waveform should be taken before the center of the eye pattern, at the center of the eye pattern, or after the center of the eye pattern and by what time change. Accordingly, a single low power clock can be utilized to adjust the timing of the sample clock such that improved communication scan be achieved. Such a single clock system has reduced power requirements and increased accuracy.
摘要翻译： 公开了一种用于数字数据接收机的采样时钟信号控制器。 可以识别数据波形的特定位模式，并且可以分析对应于特定位模式的波形的存储时间采样以改善采样时钟信号的定时。 可以利用已知位图案上的这些“时间幅度”采样来确定数据波形上的样本是否应在眼图的中心，眼图的中心之前或眼图的中心之后 和什么时间改变。 因此，可以利用单个低功率时钟来调整采样时钟的定时，从而实现改进的通信扫描。 这种单一时钟系统降低了功率需求并提高了精度。
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公开(公告)号：US20080137790A1
公开(公告)日：2008-06-12
申请号：US11608962
申请日：2006-12-11
IPC分类号： H04L7/00
CPC分类号： H04L7/0004 , H04L7/0334
摘要： A dual mode clock and data recovery (CDR) system is disclosed. A fast locking, oversampling CDR acquisition module can begin the process to quickly create a data acquisition clock signal in start up data acquisition conditions. When at least some data can be extracted from the incoming data stream, the DRR system can indicate such stability and switch to accept control from a low power CDR maintenance module. The low power CDR maintenance module can then fine tune and maintain the timing of the data acquisition signal. If the quality of the data lock under CDR maintenance module control degrades to a sufficient degree, the high power CDR acquisition module can be re-enables and re-assert control from the low power module until such time as the lock quality is again sufficient for the low power module to be used.
摘要翻译： 公开了一种双模式时钟和数据恢复（CDR）系统。 快速锁定，过采样CDR采集模块可以开始该过程，以在启动数据采集条件下快速创建数据采集时钟信号。 当从输入数据流中提取至少一些数据时，DRR系统可以指示这种稳定性，并切换到接受来自低功率CDR维护模块的控制。 低功率CDR维护模块可以微调并保持数据采集信号的定时。 如果CDR维护模块控制下的数据锁定质量下降到足够的程度，高功率CDR采集模块可以重新启用并重新从低功率模块重新进行控制，直到锁定质量再次足够 要使用的低功耗模块。
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公开(公告)号：US20080133958A1
公开(公告)日：2008-06-05
申请号：US11566576
申请日：2006-12-04
CPC分类号： G01R31/3171 , B82Y25/00 , G01R33/093
摘要： A method and system for determining the eye pattern margin parameters of a receiver system during diagnostic testing is presented. The circuitry in the receiver's front end comprises a series of latches, XOR gates and OR gates which first provide the data samples and edge samples, i.e., data sampled at the rising or falling edge of an (edge) clock characterized by a phase delay relative to the data sampling clock. The receiver also comprises optimization circuitry for the ideal alignment of the edge clock (edges) with the data edges. The method further provides for a phase shifting of the edge clock to the left and right from the ideal/locked position to screen the data eye pattern in order to compute the Bit Error Rate (BER) value. The position of the edge clock relative to the data sampling clock determines the horizontal eye opening for the computed BER.
摘要翻译： 提出了一种用于在诊断测试期间确定接收机系统的眼图边缘参数的方法和系统。 接收机前端的电路包括一系列锁存器，XOR门和OR门，它们首先提供数据样本和边缘样本，即在（边沿）时钟的上升沿或下降沿采样的数据，其特征在于相位延迟相对 到数据采样时钟。 接收机还包括用于边缘时钟（边缘）与数据边缘的理想对准的优化电路。 该方法还提供了边缘时钟从理想/锁定位置向左和向右移相以屏蔽数据眼图，以便计算误码率（BER）值。 边缘时钟相对于数据采样时钟的位置决定了计算的BER的水平眼睛开度。
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公开(公告)号：US20080137789A1
公开(公告)日：2008-06-12
申请号：US11608948
申请日：2006-12-11
CPC分类号： H04L7/042 , H04L7/0004 , H04L7/0334
摘要： A sampling clock signal controller for receivers of digital data is disclosed. Specific bit patterns of a data waveform can be identified, and stored time samples of the waveform that correspond to the specific bit patterns can be analyzed to improve the timing of a sampling clock signal. These “time-amplitude” samples on known bit patterns can be utilized to determine if a sample on the data waveform should be taken before the center of the eye pattern, at the center of the eye pattern, or after the center of the eye pattern and by what time change. Accordingly, a single low power clock can be utilized to adjust the timing of the sample clock such that improved communication scan be achieved. Such a single clock system has reduced power requirements and increased accuracy.
摘要翻译： 公开了一种用于数字数据接收机的采样时钟信号控制器。 可以识别数据波形的特定位模式，并且可以分析对应于特定位模式的波形的存储时间采样以改善采样时钟信号的定时。 可以利用已知位图案上的这些“时间幅度”采样来确定数据波形上的样本是否应在眼图的中心，眼图的中心之前或眼图的中心之后 和什么时间改变。 因此，可以利用单个低功率时钟来调整采样时钟的定时，从而实现改进的通信扫描。 这种单一时钟系统降低了功率需求并提高了精度。
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7.发明授权公开(公告)号：US07961778B2
公开(公告)日：2011-06-14
申请号：US12177231
申请日：2008-07-22
CPC分类号： H04L25/03343 , H03K5/135 , H03M9/00 , H04J3/047 , H04J3/0685 , H04L7/0037 , H04L25/03885
摘要： In the context of high-speed serial links, data-dependent jitter compensation techniques performed using phase pre-distortion. Broadly contemplated is an expansion of the notion of pre-emphasis beyond conventional amplitude compensation of ISI, whereby phase pre-emphasis for compensating data-dependent jitter (DDJ) is introduced. DDJ can be addressed by exploiting the relationship between the data sequence and the timing deviation. Phase pre-emphasis improves the signal integrity with little additional power consumption in the transmitter and with no cross-talk penalty.
摘要翻译： 在高速串行链路的上下文中，使用相位预失真执行的数据相关抖动补偿技术。 广泛考虑的是将预加重的概念扩展超出ISI的常规幅度补偿，由此引入用于补偿依赖于数据的抖动（DDJ）的相位预加重。 可以通过利用数据序列与时序偏差之间的关系来解决DDJ。 相位预加重提高了信号完整性，在发射机中几乎没有额外的功耗，没有串扰。
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公开(公告)号：US07741919B2
公开(公告)日：2010-06-22
申请号：US12114285
申请日：2008-05-02
IPC分类号： H03L7/00
CPC分类号： H03L7/0893 , H03L7/093 , H03L7/0998 , H03L2207/06
摘要： A voltage controlled oscillator and a method of operating a voltage-controlled oscillator are disclosed. The oscillator comprises a current controlled oscillator having a variable frequency current output, a first control path for generating a first control current having a first adjustable gain, and a second control path for generating a second control current having a second adjustable gain. A summer is provided for adding the first and second control currents to obtain a summed control current, and for applying the summed control current as an input current to the current controlled oscillator. A control sub-circuit is used for controlling the gain of the first control current as a function of a defined voltage on the second control path to maintain constant the gain of the current output of the current controlled oscillator over a given operating range of the current controlled oscillator.
摘要翻译： 公开了压控振荡器和操作压控振荡器的方法。 振荡器包括具有可变频率电流输出的电流控制振荡器，用于产生具有第一可调增益的第一控制电流的第一控制路径和用于产生具有第二可调增益的第二控制电流的第二控制路径。 提供一个加法器，用于增加第一和第二控制电流以获得相加的控制电流，并且将求和的控制电流作为输入电流施加到电流控制的振荡器。 控制子电路用于控制作为第二控制路径上的限定电压的函数的第一控制电流的增益，以在电流的给定工作范围内保持电流控制振荡器的电流输出的增益恒定 受控振荡器。
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9.发明申请公开(公告)号：US20080298530A1
公开(公告)日：2008-12-04
申请号：US12177231
申请日：2008-07-22
IPC分类号： H04L7/00
CPC分类号： H04L25/03343 , H03K5/135 , H03M9/00 , H04J3/047 , H04J3/0685 , H04L7/0037 , H04L25/03885
摘要： In the context of high-speed serial links, data-dependent jitter compensation techniques performed using phase pre-distortion. Broadly contemplated is an expansion of the notion of pre-emphasis beyond conventional amplitude compensation of ISI, whereby phase pre-emphasis for compensating data-dependent jitter (DDJ) is introduced. DDJ can be addressed by exploiting the relationship between the data sequence and the timing deviation. Phase pre-emphasis improves the signal integrity with little additional power consumption in the transmitter and with no cross-talk penalty.
摘要翻译： 在高速串行链路的上下文中，使用相位预失真执行的数据相关抖动补偿技术。 广泛考虑的是将预加重的概念扩展超出ISI的常规幅度补偿，由此引入用于补偿依赖于数据的抖动（DDJ）的相位预加重。 可以通过利用数据序列与时序偏差之间的关系来解决DDJ。 相位预加重提高了信号完整性，在发射机中几乎没有额外的功耗，没有串扰。
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10.发明申请公开(公告)号：US20090273405A1
公开(公告)日：2009-11-05
申请号：US12114285
申请日：2008-05-02
IPC分类号： H03L5/00
CPC分类号： H03L7/0893 , H03L7/093 , H03L7/0998 , H03L2207/06
摘要： A voltage controlled oscillator and a method of operating a voltage-controlled oscillator are disclosed. The oscillator comprises a current controlled oscillator having a variable frequency current output, a first control path for generating a first control current having a first adjustable gain, and a second control path for generating a second control current having a second adjustable gain. A summer is provided for adding the first and second control currents to obtain a summed control current, and for applying the summed control current as an input current to the current controlled oscillator. A control sub-circuit is used for controlling the gain of the first control current as a function of a defined voltage on the second control path to maintain constant the gain of the current output of the current controlled oscillator over a given operating range of the current controlled oscillator.
摘要翻译： 公开了压控振荡器和操作压控振荡器的方法。 振荡器包括具有可变频率电流输出的电流控制振荡器，用于产生具有第一可调增益的第一控制电流的第一控制路径和用于产生具有第二可调增益的第二控制电流的第二控制路径。 提供一个加法器，用于增加第一和第二控制电流以获得相加的控制电流，并且将求和的控制电流作为输入电流施加到电流控制的振荡器。 控制子电路用于控制作为第二控制路径上的限定电压的函数的第一控制电流的增益，以在电流的给定工作范围内保持电流控制振荡器的电流输出的增益恒定 受控振荡器。
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