公开(公告)号：US07142624B2

公开(公告)日：2006-11-28

申请号：US11225600

申请日：2005-09-13

申请人： Hayden Clavie Cranford, Jr. ,  Stacy Jean Garvin ,  Vernon Roberts Norman ,  Paul Alan Owczarski ,  Martin Leo Schmatz ,  Joseph Marsh Stevens

发明人： Hayden Clavie Cranford, Jr. ,  Stacy Jean Garvin ,  Vernon Roberts Norman ,  Paul Alan Owczarski ,  Martin Leo Schmatz ,  Joseph Marsh Stevens

IPC分类号： H03D3/24

CPC分类号： H03L7/0995 ,  H04L7/0004 ,  H04L7/0337

摘要： The present analog invention is related to a unified digital architecture comprising logic transmitter portions and logic receiver portions. A unified serial link system and method for transmitting digital data across wired media including a transmitter and a receiver portion is provided, one of the transmitter portion and receiver portion comprising a phase locked loop (PLL) circuit. The PLL circuit comprises a voltage control oscillator, a frequency divider, a phase-frequency detector, a charge pump and a multi-pole loop filter. One embodiment comprises a dual loop PLL having a digital coarse loop and an analog fine loop.

公开(公告)号：US06993107B2

公开(公告)日：2006-01-31

申请号：US09996053

申请日：2001-11-28

申请人： Hayden Clavie Cranford, Jr. ,  Stacy Jean Garvin ,  Vernon Roberts Norman ,  Paul Alan Owczarski ,  Martin Leo Schmatz ,  Joseph Marsh Stevens

发明人： Hayden Clavie Cranford, Jr. ,  Stacy Jean Garvin ,  Vernon Roberts Norman ,  Paul Alan Owczarski ,  Martin Leo Schmatz ,  Joseph Marsh Stevens

IPC分类号： H03D3/24

CPC分类号： H03L7/0995 ,  H04L7/0004 ,  H04L7/0337

摘要： A unified serial link system and method for transmitting digital data across wired media including a transmitter and a receiver. The system comprises a phase locked loop (PLL) control circuit, a phase rotator circuit, a phase buffer circuit, and an equalization driver circuit. The phase rotator circuit is configured to acquire a clock phase from the phase locked loop control circuit and modulo shift the clock phase into a desired phase angle. One embodiment comprises a dual loop PLL having a digital coarse loop and an analog fine loop, a multi-stage voltage controlled oscillator, a voltage comparator, a PLL control logic, a digital to analog counter and a low pass filter. The fine loop includes the oscillator, a frequency divider, a phase-frequency detector, a charge pump and a loop filter.