公开(公告)号：US08514953B2

公开(公告)日：2013-08-20

申请号：US11935903

申请日：2007-11-06

申请人： Hee Choul Lee ,  Chan Hong Park

发明人： Hee Choul Lee ,  Chan Hong Park

IPC分类号： H04L27/28

CPC分类号： H04B7/02 ,  H04B17/21

摘要： Techniques for writing to registers associated with MIMO signal paths are disclosed. In an embodiment, a controller writes a common value to all registers corresponding to the same operational parameter or parameters, for all signal paths in the MIMO transmitter or receiver. The controller then updates the register in any signal path whose operational paramater differs from the common value, by accumulating a value to the value already in the register, or by replacing the value already in the register with a different value.

摘要翻译： 公开了写入与MIMO信号路径相关联的寄存器的技术。 在一个实施例中，对于MIMO发射机或接收机中的所有信号路径，控制器将公共值写入对应于相同操作参数或参数的所有寄存器。 然后，控制器将其操作参数与公共值不同的任何信号路径中的寄存器进行更新，方法是将值累加到已经在寄存器中的值，或者用已经在寄存器中的值替换为不同的值。

公开(公告)号：US20090116566A1

公开(公告)日：2009-05-07

申请号：US11935903

申请日：2007-11-06

申请人： Hee Choul Lee ,  Chan Hong Park

发明人： Hee Choul Lee ,  Chan Hong Park

IPC分类号： H04L27/28

CPC分类号： H04B7/02 ,  H04B17/21

摘要： Techniques for writing to registers associated with MIMO signal paths are disclosed. In are embodiment, a controller writes a common value to all registers corresponding to the same operational parameter or parameters, for all signal paths in the MIMO transmitter or receiver. The controller then updates the register in any signal path whose operational paramater differs from the common value, by accumulating a value to the value already in the register, or by replacing the value already in the register with a different value.

摘要翻译： 公开了写入与MIMO信号路径相关联的寄存器的技术。 在实施例中，对于MIMO发射机或接收机中的所有信号路径，控制器将公共值写入对应于相同操作参数或参数的所有寄存器。 然后，控制器将其操作参数与公共值不同的任何信号路径中的寄存器进行更新，方法是将值累加到已经在寄存器中的值，或者用已经在寄存器中的值替换为不同的值。

公开(公告)号：US08266379B2

公开(公告)日：2012-09-11

申请号：US10453226

申请日：2003-06-02

申请人： Hee Choul Lee

发明人： Hee Choul Lee

IPC分类号： G06F12/06

CPC分类号： G06F12/0842

摘要： A multithreaded processor includes multiple level-1 program caches and multiple level-1 data caches to decrease the likelihood of cache misses after thread switches. By using multiple level-1 caches, execution of a first thread does not cause instructions or data cached for a second thread to be replaced. Thus, when the second thread is being executed the occurrence of cache misses is reduced.

摘要翻译： 多线程处理器包括多个1级程序缓存和多级1数据高速缓存，以减少线程切换后高速缓存未命中的可能性。 通过使用多个1级缓存，第一个线程的执行不会导致替换第二个线程的指令或数据被缓存。 因此，当第二线程被执行时，缓存未命中的发生被减少。

公开(公告)号：US08170506B2

公开(公告)日：2012-05-01

申请号：US12181904

申请日：2008-07-29

申请人： Bahman Ahrari ,  Hee Choul Lee ,  Jin-Su Ko ,  Sang Oh Lee

发明人： Bahman Ahrari ,  Hee Choul Lee ,  Jin-Su Ko ,  Sang Oh Lee

IPC分类号： H04B1/04 ,  H04B17/00

CPC分类号： H04L25/061 ,  H04L27/364

摘要： Techniques for reducing or eliminating DC (direct current) offset in transmitters are disclosed. An apparatus for DC offset reduction may include a converter, a digital engine, and a plurality of programmable current supplies. The converter is configured to provide digital representations of a plurality of DC currents associated, respectively, with a plurality of differential signal legs. The digital engine is configured to receive the digital representations and to produce instructions for generating compensating currents for the plurality of differential signal legs based on comparisons, respectively, between each of the digital representations and a calibration current. The programmable current supplies correspond, respectively, to the differential signal legs. The current supplies are configured to inject the compensating currents into the differential signal legs, respectively, to reduce DC offset between the differential signal legs, based upon the instructions. The instructions allow one-shot DC offset correction, instead of successive approximation for DC offset correction.

摘要翻译： 公开了用于减少或消除发射机中的DC（直流）偏移的技术。 用于DC偏移减小的装置可以包括转换器，数字引擎和多个可编程电流源。 转换器被配置为提供分别与多个差分信号支路相关联的多个DC电流的数字表示。 数字引擎被配置为接收数字表示并且基于分别在每个数字表示和校准电流之间的比较来产生用于产生用于多个差分信号支路的补偿电流的指令。 可编程电流电源分别对应于差分信号支路。 当前电源被配置为分别将补偿电流注入到差分信号支路中，以基于指令减小差分信号支路之间的DC偏移。 该指令允许单次直流偏移校正，而不是逐次逼近直流偏移校正。

公开(公告)号：US20100026383A1

公开(公告)日：2010-02-04

申请号：US12181904

申请日：2008-07-29

申请人： Bahman Ahrari ,  Hee Choul Lee ,  Jin-Su Ko ,  Sang Oh Lee

发明人： Bahman Ahrari ,  Hee Choul Lee ,  Jin-Su Ko ,  Sang Oh Lee

IPC分类号： H04B1/10

CPC分类号： H04L25/061 ,  H04L27/364

摘要： Techniques for reducing or eliminating DC (direct current) offset in transmitters are disclosed. An apparatus for DC offset reduction may include a converter, a digital engine, and a plurality of programmable current supplies. The converter is configured to provide digital representations of a plurality of DC currents associated, respectively, with a plurality of differential signal legs. The digital engine is configured to receive the digital representations and to produce instructions for generating compensating currents for the plurality of differential signal legs based on comparisons, respectively, between each of the digital representations and a calibration current. The programmable current supplies correspond, respectively, to the differential signal legs. The current supplies are configured to inject the compensating currents into the differential signal legs, respectively, to reduce DC offset between the differential signal legs, based upon the instructions. The instructions allow one-shot DC offset correction, instead of successive approximation for DC offset correction.

摘要翻译： 公开了用于减少或消除发射机中的DC（直流）偏移的技术。 用于DC偏移减小的装置可以包括转换器，数字引擎和多个可编程电流源。 转换器被配置为提供分别与多个差分信号支路相关联的多个DC电流的数字表示。 数字引擎被配置为接收数字表示并且基于分别在每个数字表示和校准电流之间的比较来产生用于产生用于多个差分信号支路的补偿电流的指令。 可编程电流电源分别对应于差分信号支路。 当前电源被配置为分别将补偿电流注入到差分信号支路中，以基于指令减小差分信号支路之间的DC偏移。 该指令允许单次直流偏移校正，而不是逐次逼近直流偏移校正。