公开(公告)号：US08514953B2

公开(公告)日：2013-08-20

申请号：US11935903

申请日：2007-11-06

申请人： Hee Choul Lee ,  Chan Hong Park

发明人： Hee Choul Lee ,  Chan Hong Park

IPC分类号： H04L27/28

CPC分类号： H04B7/02 ,  H04B17/21

摘要： Techniques for writing to registers associated with MIMO signal paths are disclosed. In an embodiment, a controller writes a common value to all registers corresponding to the same operational parameter or parameters, for all signal paths in the MIMO transmitter or receiver. The controller then updates the register in any signal path whose operational paramater differs from the common value, by accumulating a value to the value already in the register, or by replacing the value already in the register with a different value.

摘要翻译： 公开了写入与MIMO信号路径相关联的寄存器的技术。 在一个实施例中，对于MIMO发射机或接收机中的所有信号路径，控制器将公共值写入对应于相同操作参数或参数的所有寄存器。 然后，控制器将其操作参数与公共值不同的任何信号路径中的寄存器进行更新，方法是将值累加到已经在寄存器中的值，或者用已经在寄存器中的值替换为不同的值。

公开(公告)号：US20120187994A1

公开(公告)日：2012-07-26

申请号：US13011716

申请日：2011-01-21

申请人： Jeongsik Yang ,  Chan Hong Park ,  Sang-oh Lee

发明人： Jeongsik Yang ,  Chan Hong Park ,  Sang-oh Lee

IPC分类号： H03K5/00

CPC分类号： H04L27/3863 ,  H03D7/1441 ,  H03D7/1458 ,  H03D7/165 ,  H03L7/0812 ,  H04L27/368

摘要： System for I-Q phase mismatch detection and correction. An apparatus to correct a phase mismatch between I and Q signals includes a correction circuit configured to continuously compare a reference signal and a phase error signal associated with the I and Q signals to generate an I bias signal and a Q bias signal, a first CMOS buffer configured to receive the I signal and the I bias signal and output a phase adjusted I signal based on the I bias signal, and a second CMOS buffer configured to receive the Q signal and the Q bias signal and output a phase adjusted Q signal based on the Q bias signal.

摘要翻译： 用于I-Q相位失配检测和校正的系统。 用于校正I和Q信号之间的相位失配的装置包括校正电路，被配置为连续地比较参考信号和与I和Q信号相关联的相位误差信号，以产生I偏置信号和Q偏置信号，第一CMOS 缓冲器，被配置为接收I信号和I偏置信号，并且基于I偏置信号输出相位调整的I信号;以及第二CMOS缓冲器，被配置为接收Q信号和Q偏置信号，并输出基于相位的Q信号 对Q偏置信号。

公开(公告)号：US08204154B2

公开(公告)日：2012-06-19

申请号：US12783012

申请日：2010-05-19

申请人： ByungWook Min ,  Chan Hong Park

发明人： ByungWook Min ,  Chan Hong Park

IPC分类号： H04L25/06 ,  H04L25/10

CPC分类号： H04B1/30

摘要： A mobile communication device comprises a plurality of receivers, a phase detection circuit, and a DC offset calibration circuit. Each receiver comprises a receiver chain and a divide-by-2 circuit that supplies Local Oscillating (LO) signal for the receiver chain. The LO signals leak to each receiver chain and create an undesirable DC offset voltage. The DC offset depends on an LNA gain and a phase relation among the LO leakages. In a first novel aspect, a two-dimensional DC offset calibration (DCOC) table is prepared for each receiver chain. In a second novel aspect, the phase detection circuit detects the phase relation among the LO leakages for each receiver chain. Based on the LNA gain and the detected phase relation of each receiver chain, a DCOC code is selected from a corresponding DCOC table such that the calibration circuit calibrates the DC offset for each receiver effectively and efficiently.

摘要翻译： 移动通信设备包括多个接收机，相位检测电路和DC偏移校准电路。 每个接收机包括一个接收器链和一个分频电路，为接收器链提供局部振荡（LO）信号。 LO信号泄漏到每个接收器链，并产生不期望的DC偏移电压。 DC偏移取决于LNA增益和LO泄漏之间的相位关系。 在第一个新颖的方面，为每个接收器链准备二维DC偏移校准（DCOC）表。 在第二个新颖的方面，相位检测电路检测每个接收器链的LO泄漏之间的相位关系。 基于LNA增益和每个接收机链的检测相位关系，从相应的DCOC表中选择DCOC码，使得校准电路有效地高效地校准每个接收机的DC偏移。

公开(公告)号：US06844761B2

公开(公告)日：2005-01-18

申请号：US10437417

申请日：2003-05-12

申请人： Sang Jin Byun ,  Beomsup Kim ,  Chan-Hong Park

发明人： Sang Jin Byun ,  Beomsup Kim ,  Chan-Hong Park

IPC分类号： H03L7/00 ,  H03L7/081 ,  H03L7/089 ,  H03L7/06

CPC分类号： H03L7/0812 ,  H03L7/0891 ,  H03L2207/14

摘要： A system and method are disclosed for providing a DLL with false lock protector to avoid false lock and ensure accurate lock. The false lock protector operates when the initial delay time between signals from an input reference clock and an output clock exceeds the lock range during operation of the DLL. The DLL with false lock protector includes a reference clock, a delay line composed of several delay cells connected in series, a phase detector, comparator for comparing phases of signals from the reference and output clocks, a determinator and a controller for controlling the delay of the delay line.

摘要翻译： 公开了一种系统和方法，用于为DLL提供假锁定保护器以避免假锁并确保准确的锁定。 假锁定保护器在操作期间从输入参考时钟和输出时钟的信号之间的初始延迟时间超过锁定范围时操作。 具有假锁定保护器的DLL包括参考时钟，由串联连接的多个延迟单元组成的延迟线，用于比较来自参考和输出时钟的信号的相位的相位检测器，比较器，用于控制延迟的延迟的控制器 延迟线。

公开(公告)号：US08854098B2

公开(公告)日：2014-10-07

申请号：US13011716

申请日：2011-01-21

申请人： Jeongsik Yang ,  Chan Hong Park ,  Sang-oh Lee

发明人： Jeongsik Yang ,  Chan Hong Park ,  Sang-oh Lee

IPC分类号： H03H11/16 ,  H03D7/14 ,  H03D7/16 ,  H03L7/081 ,  H04L27/36 ,  H04L27/38

CPC分类号： H04L27/3863 ,  H03D7/1441 ,  H03D7/1458 ,  H03D7/165 ,  H03L7/0812 ,  H04L27/368

摘要： System for I-Q phase mismatch detection and correction. An apparatus to correct a phase mismatch between I and Q signals includes a correction circuit configured to continuously compare a reference signal and a phase error signal associated with the I and Q signals to generate an I bias signal and a Q bias signal, a first CMOS buffer configured to receive the I signal and the I bias signal and output a phase adjusted I signal based on the I bias signal, and a second CMOS buffer configured to receive the Q signal and the Q bias signal and output a phase adjusted Q signal based on the Q bias signal.

摘要翻译： 用于I-Q相位失配检测和校正的系统。 用于校正I和Q信号之间的相位失配的装置包括校正电路，被配置为连续地比较参考信号和与I和Q信号相关联的相位误差信号，以产生I偏置信号和Q偏置信号，第一CMOS 缓冲器，被配置为接收I信号和I偏置信号，并且基于I偏置信号输出相位调整的I信号;以及第二CMOS缓冲器，被配置为接收Q信号和Q偏置信号，并输出基于相位的Q信号 对Q偏置信号。

公开(公告)号：US20110286553A1

公开(公告)日：2011-11-24

申请号：US12783012

申请日：2010-05-19

申请人： ByungWook Min ,  Chan Hong Park

发明人： ByungWook Min ,  Chan Hong Park

IPC分类号： H04L25/06

CPC分类号： H04B1/30

摘要： A mobile communication device comprises a plurality of receivers, a phase detection circuit, and a DC offset calibration circuit. Each receiver comprises a receiver chain and a divide-by-2 circuit that supplies Local Oscillating (LO) signal for the receiver chain. The LO signals leak to each receiver chain and create an undesirable DC offset voltage. The DC offset depends on an LNA gain and a phase relation among the LO leakages. In a first novel aspect, a two-dimensional DC offset calibration (DCOC) table is prepared for each receiver chain. In a second novel aspect, the phase detection circuit detects the phase relation among the LO leakages for each receiver chain. Based on the LNA gain and the detected phase relation of each receiver chain, a DCOC code is selected from a corresponding DCOC table such that the calibration circuit calibrates the DC offset for each receiver effectively and efficiently.

摘要翻译： 移动通信设备包括多个接收机，相位检测电路和DC偏移校准电路。 每个接收机包括一个接收器链和一个分频电路，为接收器链提供局部振荡（LO）信号。 LO信号泄漏到每个接收器链，并产生不期望的DC偏移电压。 DC偏移取决于LNA增益和LO泄漏之间的相位关系。 在第一个新颖的方面，为每个接收器链准备二维DC偏移校准（DCOC）表。 在第二个新颖的方面，相位检测电路检测每个接收器链的LO泄漏之间的相位关系。 基于LNA增益和每个接收机链的检测相位关系，从相应的DCOC表中选择DCOC码，使得校准电路有效地高效地校准每个接收机的DC偏移。

公开(公告)号：US20090174446A1

公开(公告)日：2009-07-09

申请号：US11970329

申请日：2008-01-07

申请人： Chan Hong Park

发明人： Chan Hong Park

IPC分类号： H03L7/085 ,  H03L7/08

CPC分类号： H03L7/093 ,  H03L7/0898 ,  H03L7/107 ,  H03L7/18

摘要： A method for calibrating the loop bandwidth of a phase-locked loop (PLL) is described. At least one resistor in the PLL filter is tuned in accordance with the frequency of an input reference signal. One or more capacitors in the PLL filter are tuned in accordance with the frequency of the input reference signal. Output pulses of one or more voltage controlled oscillators (VCO) are counted. A first charge pump current associated with a target loop bandwidth is counted in accordance with the counted output pulses. A Programmable charge pump current is tuned to the calculated first charge pump current.

摘要翻译： 描述了用于校准锁相环（PLL）的环路带宽的方法。 根据输入参考信号的频率，调整PLL滤波器中的至少一个电阻。 PLL滤波器中的一个或多个电容器根据输入参考信号的频率进行调谐。 对一个或多个压控振荡器（VCO）的输出脉冲进行计数。 与目标环路带宽相关联的第一电荷泵电流根据计数的输出脉冲进行计数。 可编程电荷泵电流被调谐到计算的第一电荷泵电流。

公开(公告)号：US20080230173A1

公开(公告)日：2008-09-25

申请号：US10592615

申请日：2005-03-31

申请人： Kyoo Choong Cho ,  Chan Hong Park ,  Pyung Guk Park

发明人： Kyoo Choong Cho ,  Chan Hong Park ,  Pyung Guk Park

IPC分类号： B32B37/02

CPC分类号： H01J11/44 ,  G02B5/20 ,  H01J9/205 ,  H01J11/10 ,  H01J2211/446 ,  H05K9/0096

摘要： A plasma display panel (PDP) filter having a high transparency and no exterior defect can be simply prepared by a method comprising the steps of a) laminating a conductive mesh film having a metallic mesh layer formed on a base film, on a transparent glass substrate such that the base film of the conductive mesh film comes in contact with the transparent glass substrate, to obtain laminate A; b) forming a transparent adhesive layer on one surface of an optic film, to obtain laminate B; c) laminating laminate A and laminate B such that the adhesive layer of laminate B comes in contact with the metallic mesh layer of laminate A, to obtain laminate C; and d) heating and pressing laminate C in an autoclave to allow the adhesive layer of laminate B attach to the metallic mesh layer of laminate A.

摘要翻译： 具有高透明度和无外部缺陷的等离子体显示面板（PDP）滤光片可以通过以下方法简单地制备：包括以下步骤：a）将形成在基膜上的金属网层的导电网膜层压在透明玻璃基板上 使得导电性网膜的基膜与透明玻璃基板接触，得到层叠体A; b）在光学膜的一个表面上形成透明粘合剂层，以获得层压体B; c）层叠层叠体A和层叠体B，使得层压体B的粘合层与层叠体A的金属网层接触，得到层叠体C; 和d）在高压釜中加热和压制层压体C以使层压体B的粘合剂层附着到层压体A的金属网层上。

公开(公告)号：US06952126B2

公开(公告)日：2005-10-04

申请号：US10438178

申请日：2003-05-13

申请人： Sang Jin Byun ,  Beomsup Kim ,  Chan-Hong Park

发明人： Sang Jin Byun ,  Beomsup Kim ,  Chan-Hong Park

IPC分类号： H03L7/089 ,  H03L7/06

CPC分类号： H03L7/0895

摘要： A technique is disclosed for providing a charge pump circuit for phase locked loop (PLL) to reduce mismatch of up/down currents and feed-through of up/down currents to voltage output. Elimination of feed-through of the input signal may be achieved by using differential switches (M1 and M2, and M3 and M4) based on DC reference voltage in the charge pump and also eliminate the mismatch of up/down currents in a wide voltage output range by applying a new replica biasing using feedback.

摘要翻译： 公开了一种用于提供用于锁相环（PLL）的电荷泵电路的技术，以减少上/下电流的失配和上/下电流的馈通到电压输出。 可以通过使用基于电荷泵中的直流参考电压的差分开关（M 1和M 2，以及M 3和M 4）来消除输入信号的馈通，并且还消除了电荷泵中的上/下电流的失配 通过使用反馈应用新的副本偏移来实现宽电压输出范围。

公开(公告)号：US08019564B2

公开(公告)日：2011-09-13

申请号：US11970329

申请日：2008-01-07

申请人： Chan Hong Park

发明人： Chan Hong Park

IPC分类号： G06F3/00

CPC分类号： H03L7/093 ,  H03L7/0898 ,  H03L7/107 ,  H03L7/18

摘要： A method for calibrating the loop bandwidth of a phase-locked loop (PLL) is described. At least one resistor in the PLL filter is tuned in accordance with the frequency of an input reference signal. One or more capacitors in the PLL filter are tuned in accordance with the frequency of the input reference signal. Output pulses of one or more voltage controlled oscillators (VCO) are counted. A first charge pump current associated with a target loop bandwidth is counted in accordance with the counted output pulses. A programmable charge pump current is tuned to the calculated first charge pump current.

摘要翻译： 描述了用于校准锁相环（PLL）的环路带宽的方法。 根据输入参考信号的频率，调整PLL滤波器中的至少一个电阻。 PLL滤波器中的一个或多个电容器根据输入参考信号的频率进行调谐。 对一个或多个压控振荡器（VCO）的输出脉冲进行计数。 与目标环路带宽相关联的第一电荷泵电流根据计数的输出脉冲进行计数。 可编程电荷泵电流被调谐到计算的第一电荷泵电流。