公开(公告)号：US07335884B2

公开(公告)日：2008-02-26

申请号：US11327461

申请日：2006-01-09

申请人： Hee Chul Lee ,  Chi Ho Hwang ,  Yong Soo Lee ,  Sang Gu Kang

发明人： Hee Chul Lee ,  Chi Ho Hwang ,  Yong Soo Lee ,  Sang Gu Kang

IPC分类号： G01J5/02

CPC分类号： G01J5/24 ,  H04N5/33 ,  H04N5/3651 ,  H04N5/3655

摘要： The present invention relates to a bolometer, and more specifically to a compensation circuit for compensating non-uniformity due to the difference of operating temperature between bolometers which exist in bolometer array using semiconductor material. A compensation circuit according to the present invention comprises a biasing part including a first transistor generating bias current according to the change of operating temperature to have a dependency of exponential function for the operating temperature of circuit, and a second transistor turned on/off according to the column signal of a bolometer array; a bolometer part including a variable resistor for detecting IR in a pixel base, a third transistor turned on/off according to the column signal of a bolometer array coupled to one end of the variable resistor, and a fourth transistor turned on/off according to the row signal of a bolometer array coupled to the other end of the variable resistor; and an off-set compensation part for compensating the non-uniformity of the bolometer unit.

摘要翻译： 本发明涉及测辐射热计，更具体地说，涉及一种用于补偿不均匀性的补偿电路，这是由于存在于使用半导体材料的测辐射热计阵列中的测辐射热量计之间的工作温度差异。 根据本发明的补偿电路包括偏置部分，其包括第一晶体管，根据工作温度的变化产生偏置电流，以使电路的工作温度具有指数函数的依赖性，并且根据第 测辐射热计阵列的列信号; 一个测辐射热计部分，包括用于检测像素基础中的IR的可变电阻器，根据耦合到可变电阻器的一端的测辐射热计阵列的列信号导通/关断第三晶体管，以及第四晶体管根据 耦合到可变电阻器的另一端的测辐射热计阵列的行信号; 以及用于补偿测辐射热计单元的不均匀性的偏移补偿部分。

公开(公告)号：US08493784B2

公开(公告)日：2013-07-23

申请号：US13597624

申请日：2012-08-29

申请人： Sang Gu Kang

发明人： Sang Gu Kang

IPC分类号： G11C7/10

CPC分类号： G11C11/5628 ,  G11C16/3454 ,  G11C2211/5621

摘要： A method of programming a nonvolatile memory device comprises applying a program voltage to a selected wordline to program selected memory cells, and performing a verify operation by applying a verify voltage to the selected wordline to determine the programming status of the selected memory cells. The verify operation applies the verify voltage to the selected wordline at least two different times to divide the selected memory cells into at least three regions corresponding to different threshold voltage ranges.

摘要翻译： 一种对非易失性存储器件进行编程的方法包括将程序电压施加到所选择的字线以编程所选择的存储器单元，以及通过对所选择的字线施加验证电压来执行验证操作，以确定所选存储器单元的编程状态。 验证操作将验证电压施加到所选择的字线至少两个不同的时间，以将所选择的存储器单元划分成对应于不同阈值电压范围的至少三个区域。

公开(公告)号：US08120967B2

公开(公告)日：2012-02-21

申请号：US12730525

申请日：2010-03-24

申请人： Sang Gu Kang

发明人： Sang Gu Kang

IPC分类号： G11C16/06

CPC分类号： G11C11/5628 ,  G11C16/3454 ,  G11C2211/5621

摘要： A method of programming a nonvolatile memory device comprises applying a program voltage to a selected wordline to program selected memory cells, and performing a verify operation by applying a verify voltage to the selected wordline to determine the programming status of the selected memory cells. The verify operation applies the verify voltage to the selected wordline at least two different times to divide the selected memory cells into at least three regions corresponding to different threshold voltage ranges.

公开(公告)号：US20070223273A1

公开(公告)日：2007-09-27

申请号：US11715365

申请日：2007-03-08

申请人： Sang Gu Kang ,  Yun Seung Shin

发明人： Sang Gu Kang ,  Yun Seung Shin

IPC分类号： G11C16/06

CPC分类号： G11C16/0483

摘要： A non-volatile semiconductor memory device includes a memory array having a cell string. The cell string includes a plurality of normal memory cells, a ground selection transistor gated so as to provide a source voltage to the normal memory cells, at least two dummy cells connected between a normal memory cell on one side end of the cell string and the ground selection transistor, wherein the normal memory cells are configured to store data and the dummy cells are configured to not store data. The memory device also includes a word line selection block which controls normal word lines to gate the normal memory cells and dummy word lines to gate the dummy cells, wherein the dummy word lines are controlled as sequential voltage levels during a program operation to select the normal memory cell on the one side end.

摘要翻译： 非易失性半导体存储器件包括具有单元串的存储器阵列。 单元串包括多个正常存储单元，选通晶体管，以便向正常存储单元提供源电压，至少两个虚拟单元连接在单元串的一侧端的正常存储单元和 接地选择晶体管，其中所述正常存储器单元被配置为存储数据，并且所述虚拟单元被配置为不存储数据。 存储装置还包括字线选择块，其控制正常字线以选通正常存储器单元和虚拟字线以对虚拟单元进行栅极，其中在编程操作期间将虚拟字线控制为顺序电压电平以选择正常 存储单元在一端。

公开(公告)号：US08279680B2

公开(公告)日：2012-10-02

申请号：US13351580

申请日：2012-01-17

申请人： Sang Gu Kang

发明人： Sang Gu Kang

IPC分类号： G11C16/06

CPC分类号： G11C11/5628 ,  G11C16/3454 ,  G11C2211/5621

摘要： A method of programming a nonvolatile memory device comprises applying a program voltage to a selected wordline to program selected memory cells, and performing a verify operation by applying a verify voltage to the selected wordline to determine the programming status of the selected memory cells. The verify operation applies the verify voltage to the selected wordline at least two different times to divide the selected memory cells into at least three regions corresponding to different threshold voltage ranges.

摘要翻译： 一种对非易失性存储器件进行编程的方法包括将程序电压施加到所选择的字线以编程所选择的存储器单元，以及通过对所选择的字线施加验证电压来执行验证操作，以确定所选存储器单元的编程状态。 验证操作将验证电压施加到所选择的字线至少两个不同的时间，以将所选择的存储器单元划分成对应于不同阈值电压范围的至少三个区域。

公开(公告)号：US07652926B2

公开(公告)日：2010-01-26

申请号：US11715365

申请日：2007-03-08

申请人： Sang Gu Kang ,  Yun Seung Shin

发明人： Sang Gu Kang ,  Yun Seung Shin

IPC分类号： G11C16/06

CPC分类号： G11C16/0483

摘要： A non-volatile semiconductor memory device includes a memory array having a cell string. The cell string includes a plurality of normal memory cells, a ground selection transistor gated so as to provide a source voltage to the normal memory cells, at least two dummy cells connected between a normal memory cell on one side end of the cell string and the ground selection transistor, wherein the normal memory cells are configured to store data and the dummy cells are configured to not store data. The memory device also includes a word line selection block which controls normal word lines to gate the normal memory cells and dummy word lines to gate the dummy cells, wherein the dummy word lines are controlled as sequential voltage levels during a program operation to select the normal memory cell on the one side end.

摘要翻译： 非易失性半导体存储器件包括具有单元串的存储器阵列。 单元串包括多个正常存储单元，选通晶体管，以便向正常存储单元提供源电压，至少两个虚拟单元连接在单元串的一侧端的正常存储单元和 接地选择晶体管，其中所述正常存储器单元被配置为存储数据，并且所述虚拟单元被配置为不存储数据。 存储装置还包括字线选择块，其控制正常字线以选通正常存储器单元和虚拟字线以对虚拟单元进行栅极，其中在编程操作期间将虚拟字线控制为顺序电压电平以选择正常 存储单元在一端。