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公开(公告)号：US20240395205A1
公开(公告)日：2024-11-28
申请号：US18693528
申请日：2023-08-02
Inventor： Jian MAO , Song MENG , Xiaolong WEI , Miao LIU , Cheng XU
IPC: G09G3/3233 , G09G3/00
Abstract: The display panel includes a plurality of pixel units and a sense compensation circuit; and a pixel unit includes a plurality of sub-pixels; a sub-pixel includes a pixel drive circuit and an element to be driven; the display panel further includes: a detection unit and a compensator; the sense compensation circuit is configured to sense the electrical characteristics of said element at a non-active time; the detection unit is configured to detect whether dynamic and static attributes of a picture displayed in a previous preset time period are changed, and send a first notification to the compensator when the dynamic and static attributes are changed; the compensator is configured to receive the first notification and not, according to the sense result of the sense compensation circuit in the previous preset time period, compensate for a picture displayed in a next preset time period.
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公开(公告)号：US20240395201A1
公开(公告)日：2024-11-28
申请号：US18272811
申请日：2022-07-29
Inventor： Zhidong YUAN , Yongqian LI , Can YUAN , Liu WU , Xiuting LIU , Luke DING , Cheng XU , Miao LIU , Xing YAO
IPC: G09G3/3233 , G11C19/28 , H10K59/131
Abstract: A display substrate and a display apparatus. The display substrate includes a display area provided with pixel circuits arranged in an array and a non-display area provided with M light emitting driving circuits, M control driving circuits and M reset driving circuits. Odd-numbered light emitting driving circuits are electrically connected with first and second light emitting clock signal lines, and even-numbered light emitting driving circuits are connected with third and fourth light emitting clock signal lines; and/or, odd-numbered control driving circuits are electrically connected with first and second control clock signal lines, and even-numbered control driving circuits are connected with third and fourth control clock signal lines; and/or, odd-numbered reset driving circuits are electrically connected with first and second reset clock signal lines, and even-numbered reset driving circuits are connected with third and fourth reset clock signal lines.
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公开(公告)号：US20240386845A1
公开(公告)日：2024-11-21
申请号：US18033589
申请日：2022-06-29
Inventor： Zhidong YUAN , Cheng XU , Dacheng ZHANG , Can YUAN , Xiuting LIU , Yongqian LI
IPC: G09G3/3233
Abstract: The present disclosure provides a signal selection circuit and a signal selection method of a display panel, and a display device. The display panel has N regions and includes pixel driving circuits and M gate driving circuits for providing M gate driving signals to the pixel driving circuits; each gate driving circuit includes N gate driving sub-circuits, each of which is configured to provide one gate driving signal to the pixel driving circuits in one region; M≥2, N≥2, and M and N are integers; the signal selection circuit includes: M frame start signal lines, each of which is configured to provide a frame start signal for one gate driving circuit; and a selection sub-circuit configured to output frame start signals written by the frame start signal lines to the gate driving sub-circuits corresponding to the regions of the display panel according to a preset sequence.
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公开(公告)号：US20240321195A1
公开(公告)日：2024-09-26
申请号：US18257385
申请日：2022-06-24
IPC: G09G3/3225 , G02F1/1345 , G09G3/32 , G09G3/36 , H10K59/126 , H10K59/131
CPC classification number: G09G3/3225 , G02F1/13452 , G09G3/32 , G09G3/3648 , H10K59/126 , H10K59/131 , G09G2300/0426 , G09G2310/0291 , G09G2320/0219 , G09G2370/14
Abstract: A display module includes a display panel, at least one bonding circuit board, a plurality of chip-on-films, and a plurality of buffer devices. The at least one bonding circuit board each include first differential lines, and a first differential line includes a P-polarity differential sub-line and an N-polarity differential sub-line. An end of a chip-on-film is connected to the first differential line, and the other end of the chip-on-film is connected to the display panel. The buffer devices are arranged on the bonding circuit board, a buffer device is connected to ends, proximate to the chip-on-film, of the P-polarity differential sub-line and the N-polarity differential sub-line, and the buffer device is configured to reduce signal reflection between the first differential line and the chip-on-film.
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公开(公告)号：US20240363050A1
公开(公告)日：2024-10-31
申请号：US18029107
申请日：2022-06-29
IPC: G09G3/20 , G09G3/3233
CPC classification number: G09G3/2092 , G09G3/3233 , G09G2300/0842 , G09G2320/0257 , G09G2320/045
Abstract: Provided are a timing controller, sensing compensation method thereof, and display panel. The timing controller includes a sensing module (501), a built-in picture generation module (502), a multi-channel data selection module (503) and a processing output module (504). The sensing module is configured to sense whether a sensing compensation instruction is received, when received, notify built-in picture generation module and multi-channel data selection module; built-in picture generation module is configured to receive a notification and generate a first video signal; multi-channel data selection module is configured to receive a notification, switch from a display mode to a built-in picture mode, select first video signal as a video source, output first video signal to processing output module; processing output module is configured to process first video signal and output processed first video signal to the display panel so that the display panel performs sensing compensation based on the first video signal.
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Patent Agency Ranking
公开(公告)号：US20240321198A1
公开(公告)日：2024-09-26
申请号：US18034374
申请日：2022-06-29
Inventor： Min HE , Xiaolong WEI , Song MENG , Qiang FEI , Jingbo XU , Cheng XU , Miao LIU , Pengfei YIN
IPC: G09G3/3233 , G09G3/20
CPC classification number: G09G3/3233 , G09G3/2096 , G09G2300/0819 , G09G2300/0842 , G09G2320/103
Abstract: Disclosed are a display panel and a display method thereof, and a display apparatus. The display panel includes multiple pixel units, a pixel unit includes multiple sub-pixels, a sub-pixel includes a pixel drive circuit, a sense compensation circuit, and an element to be driven, and the display panel further includes a detection unit and a compensator; the pixel drive circuit is configured to drive the element to be driven in active time; the sense compensation circuit is configured to sense electrical characteristics of the element to be driven in blank time; the detection unit is configured to detect whether a currently displayed picture is a still picture, send a first notification to the compensator when the currently displayed picture is a still picture, and send a second notification to the compensator when the currently displayed picture is a non-still picture.
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公开(公告)号：US20250006121A1
公开(公告)日：2025-01-02
申请号：US18275228
申请日：2022-07-28
IPC: G09G3/3225 , G09G3/32
Abstract: Provided is a compensation method for a display device. The method includes: acquiring first detection voltages of the plurality of subpixels during a first shutdown compensation process; acquiring first position indication information based on the first detection voltages of the plurality of subpixels; and determining first compensation data based on the first position indication information. The first position indication information indicates column positions of pixels to which a plurality of first subpixels of the plurality of subpixels belong. The first compensation data includes first threshold compensation voltages of the plurality of subpixels, and an absolute value of a difference between the first threshold compensation voltage of the first subpixel and a first reference value is less than an absolute value of a difference between a second threshold compensation voltage of the first subpixel in the first compensation data and the first reference value.
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公开(公告)号：US20240402966A1
公开(公告)日：2024-12-05
申请号：US18261152
申请日：2022-06-29
Inventor： Xiaolong WEI , Wenchao BAO , Song MENG , Yao ZHANG , Miao LIU , Cheng XU , Jingbo XU
IPC: G06F3/14
Abstract: A display device includes: a display screen, a drive circuit, a first controller and a second controller. The display screen includes a first display region and a second display region. The drive circuit is configured to transmit a control signal to at least one of the first controller or the second controller. The first controller is configured to, responding to the control signal, perform a display control on the first display region. The second controller is configured to, responding to the control signal, perform a display control on the second display region. A display time difference between the first display region and the second display region is less than a threshold time period.
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公开(公告)号：US20240397650A1
公开(公告)日：2024-11-28
申请号：US18696957
申请日：2023-07-04
IPC: H05K5/02
Abstract: The present disclosure provides a display substrate and a display device. The display substrate includes: a base substrate including a display area and a first frame area located on one side of the display area; and a first power bus at least located in the first frame area. The first power bus includes a first sub-bus, a second sub-bus and at least two connecting wires. The first sub-bus is located between the second sub-bus and the display area, and the first sub-bus is electrically connected to the second sub-bus by means of the at least two connecting wires.
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公开(公告)号：US20250014520A1
公开(公告)日：2025-01-09
申请号：US18272595
申请日：2022-07-28
Inventor： Zhidong YUAN , Yongqian LI , Can YUAN , Liu WU , Luke DING , Cheng XU , Miao LIU , Xing YAO
IPC: G09G3/3266 , G11C19/28
Abstract: Provided is a gate driver circuit. The gate driver circuit is applicable to a display panel, wherein the display panel includes a plurality of rows of pixels; the gate driver circuit including at least one gate driver sub-circuit; wherein the gate driver sub-circuit includes: at least two shift register groups, wherein each shift register group includes a plurality of shift register units; at least two first dummy units, wherein the at least two first dummy units are respectively coupled to a same input enable terminal and the at least two shift register groups; and at least two second dummy units, wherein the at least two second dummy units are coupled to the at least two shift register groups.
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