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公开(公告)号：US06732249B1
公开(公告)日：2004-05-04
申请号：US09590892
申请日：2000-06-09
IPC分类号： G06F1206
CPC分类号： G06F12/0284 , G06F12/1081
摘要： The present application is directed to a method and system for mapping a host computer address space into a network interface adapter (NIA) address space. A network interface processor contained within the NIA requests a memory allocation from the host computer. The host computer responds with an assigned base address in the host computer address space and a length defining the contiguous addresses within the host computer address space equal to the allocation requested by the NIA processor. A hardware trap is set, such that, an interrupt to the NIA processor is generated when the host computer attempts to access data at an address within the allocated address range of host computer contiguous addresses. The network interface processor translates the received host address to a physical address within the NIA address space, reads the data at the respective NIA physical address and transfers the data to the host computer.
摘要翻译： 本申请涉及用于将主计算机地址空间映射到网络接口适配器（NIA）地址空间的方法和系统。 NIA中包含的网络接口处理器请求从主机计算机的内存分配。 主计算机在主计算机地址空间中以分配的基地址进行响应，并且定义等于由NIA处理器请求的分配的主计算机地址空间内的连续地址的长度。 设置硬件陷阱，使得当主计算机尝试访问主机连续地址的分配的地址范围内的地址的数据时，产生对NIA处理器的中断。 网络接口处理器将接收到的主机地址转换为NIA地址空间内的物理地址，读取相应NIA物理地址处的数据并将数据传送到主计算机。
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公开(公告)号：US06842790B2
公开(公告)日：2005-01-11
申请号：US10836852
申请日：2004-04-30
CPC分类号： G06F12/0284 , G06F12/1081
摘要： A system and method of mapping a host computer address space into a network interface adapter (NIA) address space. A network interface processor within the NIA requests a memory allocation from the host computer. The host computer responds with an assigned base address in the host computer address space, and a length defining the contiguous addresses within the host computer address space equal to the allocation requested by the NIA processor. A hardware trap is set such that an interrupt to the NIA processor is generated when the host computer attempts to access data at an address within the allocated address range of host computer contiguous addresses. The network interface processor translates the received host address to a physical address within the NIA address space, reads the data at the respective NIA physical address, and transfers the data to the host computer.
摘要翻译： 将主机地址空间映射到网络接口适配器（NIA）地址空间的系统和方法。 NIA内的网络接口处理器请求从主机计算机的内存分配。 主计算机用主计算机地址空间中的分配的基地址进行响应，并且定义主计算机地址空间内相邻于NIA处理器请求的分配的连续地址的长度。 设置硬件陷阱，使得当主计算机尝试访问主机连续地址的分配的地址范围内的地址的数据时，产生对NIA处理器的中断。 网络接口处理器将接收到的主机地址转换为NIA地址空间内的物理地址，读取相应NIA物理地址的数据，并将数据传送到主计算机。
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3.发明授权Slave processor to slave memory data transfer with master processor writing address to slave memory and providing control input to slave processor and slave memory 失效从处理器到从属存储器数据传输，主处理器将地址写入从属存储器，并向从属处理器和从属存储器提供控制输入公开(公告)号：US06363444B1
公开(公告)日：2002-03-26
申请号：US09464626
申请日：1999-12-17
IPC分类号： G06F1300
CPC分类号： G06F13/28
摘要： A master processor, such as a processor embedded in a network interface card, is coupled to a memory via a memory data bus. The master processor generates addresses for the memory and controls the reading and writing of the memory at addressed locations. A slave processor, such as an optional encryption engine, has a data input/output bus connected to the memory data bus. The master processor also controls the reading and writing of data to/from the slave processor via the memory data bus. The master processor effects data transfers from the memory to the slave processor over the data bus by generating a series of memory addresses to read the data from the memory onto the data bus. As each data word appears on the data bus, it is written into the slave processor. The master processor effects data transfers from the slave processor to the memory over the data bus by reading a series of data from the slave processor onto the data bus, generating a series of memory addresses as the data are being read from the slave processor, and writing each data word into the memory as it appears on the data bus.
摘要翻译： 诸如嵌入在网络接口卡中的处理器的主处理器经由存储器数据总线耦合到存储器。 主处理器为存储器生成地址，并控制在寻址位置读取和写入存储器。 诸如可选加密引擎的从属处理器具有连接到存储器数据总线的数据输入/输出总线。 主处理器还通过存储器数据总线控制对从处理器的数据的读取和写入。 主处理器通过生成一系列存储器地址从数据总线上的存储器读取数据，从而从数据总线通过数据总线实现从存储器到从属处理器的数据传输。 当数据总线上出现每个数据字时，它将被写入从属处理器。 主处理器通过从从属处理器读取一系列数据到数据总线，通过数据总线实现从从属处理器到存储器的数据传输，当从从处理器读取数据时产生一系列存储器地址，以及 将数据字写入数据总线上显示的内存中。
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4.发明授权System and method for implementing an SMBus/I2C interface on a network interface card 有权用于在网络接口卡上实现SMBus / I2C接口的系统和方法公开(公告)号：US06874047B1
公开(公告)日：2005-03-29
申请号：US09591044
申请日：2000-06-09
CPC分类号： G06F13/4291
摘要： A system and method for implementing an SMBus/I2C interface in a computer connectable to a network. The system includes a plurality of devices communicably coupled to an SMBus. The system operates at a first clock rate when the system is awake, and at a second clock rate less than the first clock rate when the system is sleeping. At least when the system is sleeping, a first device stores data transferred via the SMBus in a register, and a second device drives the clock line of the SMBus to a low logic level while the data is stored in the register of the first device. Upon completion of the data transfer operation, the first device clears the data from the register, and the second device releases the clock line to allow it to be pulled-up by pull-up circuitry connected to the SMBus.
摘要翻译： 一种用于在可连接到网络的计算机中实现SMBus / I 2 C接口的系统和方法。 该系统包括可通信地耦合到SMBus的多个设备。 当系统清醒时，系统以第一时钟速率工作，并且在系统正在休眠时以第一时钟速率小于第一时钟速率。 至少当系统正在休眠时，第一设备将经由SMBus传送的数据存储在寄存器中，并且第二设备将SMBus的时钟线驱动到低逻辑电平，同时将数据存储在第一设备的寄存器中。 完成数据传输操作后，第一个设备从寄存器中清除数据，第二个设备释放时钟线，以允许其通过与SMBus相连的上拉电路进行上拉。
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