公开(公告)号：US4429383A

公开(公告)日：1984-01-31

申请号：US225736

申请日：1981-01-16

申请人： Herbert Finck ,  Konrad Reisinger

发明人： Herbert Finck ,  Konrad Reisinger

IPC分类号： H04J3/16 ,  H04J3/24 ,  H04L1/00

CPC分类号： H04J3/1629 ,  H04J3/24 ,  H04L1/0083

摘要： In a time-division multiplexing system, data are supplied to the multiplexer with different speeds. Depending on the speed, time slot groups are allocated to the data, with the number of allocated time slots increasing with the speed. The search for groups of free time slots occurs in a fixed sequence. Data to which time slot groups at the end of the fixed sequence have been allocated, are relocated to time slot groups which have become free nearer the beginning of the sequence. The allocated time slot group for the forward transmission direction is signalled to the multiplexer of the remote station which in turn occasions a corresponding allocation of time slots for the reverse transmission direction for data originating at the remote station.

摘要翻译： 在时分复用系统中，数据以不同的速度提供给多路复用器。 根据速度，时隙组分配给数据，分配的时隙数随速度而增加。 搜索空闲时隙的组以固定的顺序发生。 已经分配固定序列结尾的时隙组的数据被重新定位到在序列开头附近变得空闲的时隙组。 用于正向传输方向的所分配的时隙组被发送给远程站的多路复用器，而远端站的多路复用器反过来又对来自远程站的数据的反向传输方向的时隙进行相应的分配。

公开(公告)号：US4242750A

公开(公告)日：1980-12-30

申请号：US947653

申请日：1978-10-02

申请人： Herbert Finck ,  Konrad Reisinger

发明人： Herbert Finck ,  Konrad Reisinger

IPC分类号： H04B17/40 ,  H04L1/24 ,  H04L17/00

CPC分类号： H04L1/24 ,  H04B17/408

摘要： A process for testing a data transmission system by which data are transmitted by way of two data transmission links and by way of a first transmission device and a second transmission device provides that a test loop is closed, in dependence upon a loop signal, and a transmission section is tested. Data are transmitted in data blocks and each block includes a status bit, a synchronizing bit and n data bits. The loop signal is formed from a given combination of the status bit and data bits, and at least one of the data bits is inverted before being returned to the second transmission device.

摘要翻译： 用于测试通过两个数据传输链路并通过第一传输设备和第二传输设备传输数据的数据传输系统的过程提供了根据环路信号关闭测试环路，以及 传输部分进行测试。 数据在数据块中发送，每个块包括状态位，同步位和n个数据位。 环路信号由状态位和数据位的给定组合形成，并且至少一个数据位在返回到第二传输设备之前被反转。

公开(公告)号：US4012589A

公开(公告)日：1977-03-15

申请号：US658120

申请日：1976-02-13

申请人： Konrad Reisinger

发明人： Konrad Reisinger

IPC分类号： H04L5/22 ,  H04J3/06

CPC分类号： H04L5/225

摘要： A switching arrangement is described for transmitting data in time division multiplex (TDM) systems on a character frame basis. The system includes a polarity reversal recognition circuit producing a polarity reversal signal and signaling polarity reversals of a data signal. A blocking circuit arrangement produces a stop signal thereby blocking the polarity reversal recognition circuit throughout the duration of a predetermined number of m bits of the data signal. A clock generator produces a clock signal which facilitates the sampling of the data signal. A shift register is provided which contains no fewer than m+2 cells and has a set of parallel input terminals for the parallel coupling of binary digits to the shift register. Serial input terminals to the shift register provide for the serial application of binary digits to the shift register. A clock pulse input terminal to the shift register receives shift register clock pulses. A gate is provided for receiving the polarity reversal signal and the output signal of the last cell of the shift register. The output from the foregoing gate yields a phase position signal which is utilized to determine the phase position of the clock signal which is applied to the aforementioned clock pulse input terminal of the shift register. The output signal of the second to last cell of the shift register is applied as a stop signal to the polarity reversal recognition circuit. The phase position signal is coupled to two or more parallel input terminals of the shift register. The serial input terminals of the shift register receive binary digits differing from the binary digits of the phase position signal that are applied to the parallel input terminals of the shift register.

摘要翻译： 描述了用于以字符帧为基础在时分复用（TDM）系统中发送数据的切换装置。 该系统包括极性反转识别电路，产生极性反转信号和信令数据信号的极性反转。 阻塞电路装置产生停止信号，从而在数据信号的预定数量的m位的整个持续时间内阻止极性反转识别电路。 时钟发生器产生便于采样数据信号的时钟信号。 提供了一个移位寄存器，其包含不少于m + 2个单元，并且具有用于将二进制数字并行耦合到移位寄存器的并行输入端子的集合。 移位寄存器的串行输入端子用于向移位寄存器提供二进制数字的串行应用。 移位寄存器的时钟脉冲输入端接收移位寄存器时钟脉冲。 提供了用于接收极性反转信号和移位寄存器的最后一个单元的输出信号的门。 来自上述门的输出产生相位位置信号，该相位位置信号用于确定施加到移位寄存器的上述时钟脉冲输入端的时钟信号的相位位置。 移位寄存器的第二个到最后一个单元的输出信号作为停止信号施加到极性反转识别电路。 相位位置信号耦合到移位寄存器的两个或多个并行输入端。 移位寄存器的串行输入端子接收与施加到移位寄存器的并行输入端子的相位位置信号的二进制数字不同的二进制数字。

公开(公告)号：US4413336A

公开(公告)日：1983-11-01

申请号：US209316

申请日：1980-11-24

申请人： Charles Chaillie ,  Konrad Reisinger

发明人： Charles Chaillie ,  Konrad Reisinger

IPC分类号： H04J3/24 ,  H04J3/06

CPC分类号： H04J3/24

摘要： A process for the transmission of data from a plurality of data sources utilizes a start-stop signal whose signal frame contains one code bit and data bits from a plurality of data sources between a start bit and a stop bit. Here, the code bits indicate the assignment of the data bits to the individual data sources.

摘要翻译： 用于从多个数据源传输数据的过程利用起始停止信号，其信号帧包含来自起始位和停止位之间的多个数据源的一个码位和数据位。 这里，代码位指示将数据位分配给各个数据源。

公开(公告)号：US3985961A

公开(公告)日：1976-10-12

申请号：US559078

申请日：1975-03-17

申请人： Hans Heinrich Voss ,  Karl Georg Dieter ,  Konrad Reisinger

发明人： Hans Heinrich Voss ,  Karl Georg Dieter ,  Konrad Reisinger

IPC分类号： H04J3/06 ,  H04J3/07

CPC分类号： H04J3/07

摘要： A method for transmitting data according to time division multiplex principles is described. In each multiplex frame synchronizing bits and data bits are transmitted from a multiplexer at the transmitter over a transmission device to a multiplexer at the receiver. In each time division multiplex frame a constant number of data bits are transmitted. The synchronism of the transmitter and receiver multiplexing devices and the transmission devices located at the transmitter and receiver are established by altering the duration of the time division multiplex frame.

摘要翻译： 描述了根据时分多路复用原理发送数据的方法。 在每个多路复用帧中，同步位和数据位通过发送设备从发射机的多路复用器发送到接收机处的多路复用器。 在每个时分复用帧中，发送一定数量的数据位。 通过改变时分复用帧的持续时间来建立发射机和接收机复用设备与位于发射机和接收机的发射设备的同步。

公开(公告)号：US4213011A

公开(公告)日：1980-07-15

申请号：US932482

申请日：1978-08-10

申请人： Ludwig Hoelzl ,  Konrad Reisinger

发明人： Ludwig Hoelzl ,  Konrad Reisinger

IPC分类号： H04J3/06

CPC分类号： H04J3/0605

摘要： A process for T.D.M. frame synchronization which employs variable length synchronizing word at the receiving end and wherein the transmitter produces signals which consist of groups each comprising p bits and one marker bit and in respect to each multiplex frame contains a total of m marker bits of which s marker bits form the synchronizing words and where at the transmitter s-1 marker bits determine the following s-th marker bit and wherein the transmitted signal is stored and p+1 addresses are produced which are periodically assigned to the p bits and marker bits of each group and at the receiver the s-th bit is obtained from s-1 bits stored and compared with the corresponding received bit of the T.D.M. signal and when identity occurs pulses having a similar address are counted and a frame synchronizing signal is emitted.

摘要翻译： T.D.M.的过程 帧同步，其在接收端使用可变长度同步字，并且其中发射机产生由包括p位和一个标记位的组构成的信号，并且对于每个多路复用帧包含总共标记位形成的m个标记位 同步字和发射机s-1标记位在哪里确定下列第s标记位，并且其中发送的信号被存储，并且产生p + 1地址，周期性地分配给每个组的p位和标记位， 在接收机处，第s位从存储的s-1比特获得，并与TDM的对应的接收比特进行比较 信号和当同一性发生时具有相似地址的脉冲被计数并发出帧同步信号。

公开(公告)号：US4119795A

公开(公告)日：1978-10-10

申请号：US814895

申请日：1977-07-12

申请人： Ludwig Hoelzl ,  Joerg Maenhardt ,  Konrad Reisinger ,  Johannes Singer

发明人： Ludwig Hoelzl ,  Joerg Maenhardt ,  Konrad Reisinger ,  Johannes Singer

IPC分类号： H04L5/22

CPC分类号： H04L5/225

摘要： A circuit arrangement for facilitating the transmission of asynchronously occurring binary data values is described. According to prior art systems, each binary value change is assigned a multibit pulse group by means of channel units. These channel units require considerable technical complexity if a great many data sources are present. It is the principal object of the invention to replace the channel units by a centralized device. In accordance with the teachings of the invention, there are provided at the transmit and receive ends centralized coarse and fine time slot Raster counters and bit transition discriminators which process the pulse messages of all channels.

摘要翻译： 描述了用于促进异步发生的二进制数据值的传输的电路装置。 根据现有技术的系统，通过信道单元将每个二进制值变化分配给多位脉冲组。 如果存在大量数据源，这些通道单元需要相当的技术复杂性。 本发明的主要目的是通过集中式装置来代替信道单元。 根据本发明的教导，在发送和接收端提供集中的粗略和精细时隙光栅计数器和位转换鉴别器，其处理所有通道的脉冲消息。

公开(公告)号：US4032709A

公开(公告)日：1977-06-28

申请号：US668520

申请日：1976-03-19

申请人： Konrad Reisinger ,  Ludwig Holzl

发明人： Konrad Reisinger ,  Ludwig Holzl

IPC分类号： H04L5/24 ,  H04L5/00

CPC分类号： H04L5/24

摘要： A circuit arrangement for use in a time division multiplex (t.d.m.) data transmission system for lengthening the stop elements of data signals is described. The t.d.m. signals are transmitted via a transmission link to a receiver multiplexer. The outputs of the multiplexer are, respectively, connected by channel units to data sinks. Prior to reaching the multiplexer, however, the received data signals all pass through a central stop element lengthening device which produces a timing signal which is sequentially coupled to the channel units. The channel units, in the form of bistable stages, receive these timing signals and the information portions of the data signals, and from these establish the leading and trailing edges of the bits coupled to the respective data sinks.

公开(公告)号：US4031316A

公开(公告)日：1977-06-21

申请号：US668521

申请日：1976-03-19

申请人： Konrad Reisinger ,  Ludwig Holzl

发明人： Konrad Reisinger ,  Ludwig Holzl

IPC分类号： H04J3/06 ,  H04L5/00

CPC分类号： H04J3/0626

摘要： Apparatus is described for transmitting on a time division multiplex (t.d.m.) basis binary signals which are emitted by a plurality of data sources, each of which are connected to a multiplexer. During a cycle of operation the multiplexer establishes a conductive connection between each of its inputs, each of which is connected to a data source, and the output of the multiplexer for transmission to a receiver over a transmission link. Signals emitted from the multiplexer output are coupled to an in-phasing device which phases the individual bits into a t.d.m. signal.

摘要翻译： 描述了用于以时分多路复用（t.d.m）为基础的多个数据源发出的二进制信号进行发送的装置，每个数据源都连接到多路复用器。 在操作周期期间，多路复用器在其每个输入之间建立导电连接，每个输入连接到数据源，多路复用器的输出通过传输链路传输到接收器。 从多路复用器输出发射的信号耦合到一个定相装置，它将各个位相位分成t.d.m。 信号。

公开(公告)号：US4006302A

公开(公告)日：1977-02-01

申请号：US658121

申请日：1976-02-13

申请人： Konrad Reisinger

发明人： Konrad Reisinger

IPC分类号： H04J3/06 ,  H04L5/24 ,  H04L5/00

CPC分类号： H04L5/24 ,  H04J3/06

摘要： A switching arrangement for a data transmission system is described wherein the switching arrangement extends the receiver stop pulse length in time division multiplex transmissions of telegraph signals on a character frame basis. The character frame contains one start pulse, a number m code bits and one stop pulse. The time division multiplex (TDM) signal is applied to a first bistable circuit, and the output signal of the first bistable circuit is applied to a second bistable circuit from which a data signal is emitted to a data sink. A shift register is provided having no fewer than m+3 storage cells in which a first binary digit is stored if a stop signal is applied by means of parallel input terminals to the shift register. Timing pulses applied to the shift register are received in a pulse input. A shift register further includes a serial input terminal over which a second binary digit is read-in where no stop signal is present. A gate having inputs to which are applied the input signal of the m+3.sup.th storage cell of the shift register and the output signal of the first bistable circuit. The gate produces a stop signal. A counter is provided to which are applied the stop signal as a count signal and the output signal of the m+3.sup.th storage cell as a reset signal. The counter produces counter reading signals indicating the reading of the counter. A clock generator or more phase shifted signals are emitted in a square wave pulse form of which one half the unit element length are displaced in proper phase relation by fractions of the unit element length. Phase shifted clock signals as a function of the reading of the counter are used for timing the second bistable circuit.

摘要翻译： 描述了用于数据传输系统的切换装置，其中切换装置以字符帧为基础在电报信号的时分复用传输中扩展接收机停止脉冲长度。 字符帧包含一个起始脉冲，数字m个码位和一个停止脉冲。 时分复用（TDM）信号被施加到第一双稳态电路，并且第一双稳态电路的输出信号被施加到从数据信号发射到数据宿的第二双稳态电路。 如果通过并行输入端子向移位寄存器施加停止信号，则提供具有不少于m + 3个存储单元的移位寄存器，其中存储第一二进制数字。 施加到移位寄存器的定时脉冲在脉冲输入中被接收。 移位寄存器还包括串行输入端子，在其上读入第二二进制数位，其中不存在停止信号。 具有输入的门施加移位寄存器的第m + 3个存储单元的输入信号和第一双稳态电路的输出信号。 门产生停止信号。 提供一个计数器，将停止信号作为计数信号和第m + 3个存储单元的输出信号作为复位信号。 计数器产生指示计数器读数的计数器读取信号。 时钟发生器或更多的相移信号以矩形波脉冲形式发射，其中单位元件长度的一半以适当的相位关系移位单位元件长度的分数。 作为计数器的读取的函数的相移时钟信号用于对第二双稳态电路进行定时。