公开(公告)号：US20180004708A1

公开(公告)日：2018-01-04

申请号：US15201040

申请日：2016-07-01

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Naveen Muralimanohar ,  Ben Feinberg ,  Ali Shafiee-Ardestani

IPC: G06F17/16 ,  H03M1/66 ,  H03M1/12

CPC classification number: G06F17/16 ,  G06G7/16 ,  H03M1/12 ,  H03M1/66

Abstract: Examples herein relate to circuits for computing vector-matrix multiplications involving negative values. A first memory crossbar array may be mapped to a first matrix which includes the positive values of an input matrix. A second memory crossbar array may be mapped to a second matrix which includes the negative values of the input matrix. An analog-to-digital converter may generate digital intermediate multiplication results based on analog results computed by the memory crossbar arrays. The digital intermediate multiplication results may include an intermediate result corresponding to a multiplication of each of the first vector and second vector with each of the first matrix and the second matrix. A controller may aggregate the digital intermediate results to generate a combined multiple result that represents the vector-matrix multiplication of the input vector and the input matrix.

公开(公告)号：US09910827B2

公开(公告)日：2018-03-06

申请号：US15201040

申请日：2016-07-01

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Naveen Muralimanohar ,  Ben Feinberg ,  Ali Shafiee-Ardestani

IPC: G06G7/16 ,  G06F17/16 ,  H03M1/12 ,  H03M1/66

CPC classification number: G06F17/16 ,  G06G7/16 ,  H03M1/12 ,  H03M1/66

Abstract: Examples herein relate to circuits for computing vector-matrix multiplications involving negative values. A first memory crossbar array may be mapped to a first matrix which includes the positive values of an input matrix. A second memory crossbar array may be mapped to a second matrix which includes the negative values of the input matrix. An analog-to-digital converter may generate digital intermediate multiplication results based on analog results computed by the memory crossbar arrays. The digital intermediate multiplication results may include an intermediate result corresponding to a multiplication of each of the first vector and second vector with each of the first matrix and the second matrix. A controller may aggregate the digital intermediate results to generate a combined multiple result that represents the vector-matrix multiplication of the input vector and the input matrix.