公开(公告)号：US10698975B2

公开(公告)日：2020-06-30

申请号：US16063793

申请日：2016-01-27

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Naveen Muralimanohar ,  Benjamin Feinberg ,  John Paul Strachan

IPC: G06F17/16 ,  G11C13/00 ,  G06G7/16 ,  G11C7/16

Abstract: Example implementations of the present disclosure relate to in situ transposition of the data values in a memory array. An example system may include a non-volatile memory (NVM) array, including a plurality of NVM elements, usable in performance of computations. The example system may include an input engine to input a plurality of data values for storage by a corresponding plurality of original NVM elements. The example system may further include a transposition engine to direct performance of the in situ transposition such that the plurality of data values remains stored by the original NVM elements.

公开(公告)号：US11157237B2

公开(公告)日：2021-10-26

申请号：US16189291

申请日：2018-11-13

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Naveen Muralimanohar ,  Benjamin Feinberg

IPC: G06F7/487 ,  G06F5/01 ,  G11C13/00 ,  H03M7/24 ,  G06F17/16

Abstract: In some examples, memristive dot product circuit based floating point computations may include ascertaining a matrix and a vector including floating point values, and partitioning the matrix into a plurality of sub-matrices according to a size of a plurality of memristive dot product circuits. For each sub-matrix of the plurality of sub-matrices, the floating point values may be converted to fixed point values. Based on the conversion and selected ones of the plurality of memristive dot product circuits, a dot product operation may be performed with respect to a sub-matrix and the vector. Each ones of the plurality of memristive dot product circuits may include rows including word line voltages corresponding to the floating point values of the vector, conductances corresponding to the floating point values of an associated sub-matrix, and columns that include bitline currents corresponding to dot products of the voltages and conductances.

公开(公告)号：US20190236111A1

公开(公告)日：2019-08-01

申请号：US16063793

申请日：2016-01-27

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Naveen Muralimanohar ,  Benjamin Feinberg ,  John Paul Strachan

IPC: G06F17/16 ,  G11C13/00

CPC classification number: G06F17/16 ,  G06G7/16 ,  G11C7/16 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0069

Abstract: Example implementations of the present disclosure relate to in situ transposition of the data values in a memory array. An example system may include a non-volatile memory (NVM) array, including a plurality of NVM elements, usable in performance of computations. The example system may include an input engine to input a plurality of data values for storage by a corresponding plurality of original NVM elements. The example system may further include a transposition engine to direct performance of the in situ transposition such that the plurality of data values remains stored by the original NVM elements.