公开(公告)号：US20160113143A1

公开(公告)日：2016-04-21

申请号：US14977095

申请日：2015-12-21

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Martin Goldstein ,  Dale C. Morris ,  Michael R. Krause

IPC: H05K7/14 ,  B23P19/00

CPC classification number: H05K7/1489 ,  B23P19/00 ,  G06F1/181 ,  H04L49/40 ,  H05K7/1487 ,  H05K7/1492

Abstract: In some examples, a chassis contains a fabric module and a plurality node modules that are arranged in a plurality of rows. The fabric module is positioned in a space between a first row and a second row of the plurality of rows, and the fabric module is connected to at least two node modules of the plurality of node modules to provide communications connectivity between the at least two node modules, the chassis to accept longitudinal insertion in a longitudinal direction of the plurality of node modules and the fabric module, the fabric module being removable in the longitudinal direction from the chassis by moving the fabric module in the space between the first row and the second row without first removing the node modules in the plurality of rows.

Abstract translation: 在一些示例中，机架包含布置在多行中的结构模块和多个节点模块。 所述织物模块位于所述多个行的第一行和第二行之间的空间中，并且所述织物模块连接到所述多个节点模块的至少两个节点模块，以提供所述至少两个节点之间的通信连接 模块，所述底盘接受在所述多个节点模块和所述织物模块的纵向方向上的纵向插入，所述织物模块通过在所述第一行和第二部分之间的空间中移动所述织物模块，从所述框架沿纵向方向可移除 行，而不首先去除多行中的节点模块。

公开(公告)号：US11221967B2

公开(公告)日：2022-01-11

申请号：US14780392

申请日：2013-03-28

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Gregg B. Lesartre ,  Blaine D. Gaither ,  Dale C. Morris ,  Carey Huscroft ,  Russ W. Herrell

IPC: G06F12/08 ,  G06F12/0808 ,  G06F12/0815 ,  G06F12/14 ,  G06F12/02 ,  G06F21/79

Abstract: A system and method for addressing split modes of persistent memory are described herein. The system includes a non-volatile memory comprising regions of memory, each region comprising a range of memory address spaces. The system also includes a memory controller (MC) to control access to the non-volatile memory. The system further includes a device to track a mode of each region of memory and to define the mode of each region of memory. The mode is a functional use model.

公开(公告)号：US11126372B2

公开(公告)日：2021-09-21

申请号：US16680254

申请日：2019-11-11

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Russ W. Herrell ,  Gary Gostin ,  Gregg B Lesartre ,  Dale C. Morris

IPC: G06F3/06

Abstract: A computing system is disclosed herein. The computing system includes a computing node and a remote memory node coupled to the computing node via a system fabric. The computing node includes a plurality of processors and a master memory controller. The master memory controller is external to the plurality of processors. The master memory controller routes requests corresponding to requests from the plurality of processors across the system fabric to the remote memory node and returns a response.

公开(公告)号：US20190340053A1

公开(公告)日：2019-11-07

申请号：US15973527

申请日：2018-05-07

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Gregg B. Lesartre ,  Dale C. Morris ,  Russ W. Herrell ,  Blaine D. Gaither

IPC: G06F11/07 ,  H04L12/24

Abstract: A technique includes receiving an alert indicator in a distributed computer system that includes a plurality of computing nodes coupled together by cluster interconnection fabric. The alert indicator indicates detection of a fault in a first computing node of the plurality of computing nodes. The technique indicates regulating communication between the first computing node and at least one of the other computing nodes in response to the alert indicator to contain error propagation due to the fault within the first computing node.

公开(公告)号：US10452498B2

公开(公告)日：2019-10-22

申请号：US14901559

申请日：2013-06-28

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Gregg B. Lesartre ,  Dale C. Morris ,  Gary Gostin ,  Russ W. Herrell ,  Andrew R. Wheeler ,  Blaine D. Gaither

IPC: G06F11/00 ,  G06F11/16 ,  G06F11/10 ,  G06F11/20

Abstract: A computing system can include a processor and a persistent main memory including a fault tolerance capability. The computing system can also include a memory controller to store data in the persistent main memory and create redundant data. The memory controller can also store the redundant data remotely with respect to the persistent main memory. The memory controller can further access the redundant data during failure of the persistent main memory.