公开(公告)号：US10599598B1

公开(公告)日：2020-03-24

申请号：US16134499

申请日：2018-09-18

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Shawn K. Walker ,  Derek A. Sherlock ,  Gary Gostin

IPC: G06F13/38 ,  G06F13/40 ,  G06F13/42 ,  G06F3/06 ,  H04L29/08

Abstract: A PCIe (Peripheral Component Interconnect Express) protocol converter for connection to a central processing unit (CPU) node having a root complex, a CPU memory fabric and CPU memory may include independent PCIe links, a fabric interface and a fabric switch connected to the fabric interface. Each of the links may include an endpoint for connection to the root complex. The fabric switch is connected to the fabric interface of each of the links and is connectable to a remote node. The fabric switch transmits writes of a single write request from the remote node across both links. Each fabric interface is to transmit an acknowledgment to the remote node in response to a write of the writes becoming observable at the CPU node hi Michael, hi Michael,.

公开(公告)号：US11249918B2

公开(公告)日：2022-02-15

申请号：US16174738

申请日：2018-10-30

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Shawn K. Walker ,  Christopher Shawn Kroeger ,  Derek A. Sherlock

IPC: G06F12/1009 ,  G06F13/16 ,  G06F13/42

Abstract: A memory access system may include a first memory address translator, a second memory address translator and a mapping entry invalidator. The first memory address translator translates a first virtual address in a first protocol of a memory access request to a second virtual address in a second protocol and tracks memory access request completions. The second memory address translator is to translate the second virtual address to a physical address of a memory. The mapping entry invalidator requests invalidation of a first mapping entry of the first mapping address translator requests invalidation of a second mapping entry of the second memory address translator corresponding to the first mapping entry following invalidation of the first mapping entry and based upon the tracked memory access request completions.