公开(公告)号：US5966521A

公开(公告)日：1999-10-12

申请号：US853908

申请日：1997-05-09

申请人： Hideki Takeuchi ,  Mototaka Kuribayashi ,  Junichi Tsujimoto ,  Kentaro Kuroiwa ,  Yasuhiro Tonooka

发明人： Hideki Takeuchi ,  Mototaka Kuribayashi ,  Junichi Tsujimoto ,  Kentaro Kuroiwa ,  Yasuhiro Tonooka

IPC分类号： G01R31/28 ,  G06F17/50 ,  H01L21/82

CPC分类号： G06F17/5031

摘要： The present invention provide a system and a method for analyzing the static timing for LSIs which involves rather a small number of false paths contained in output results and also which reduces the processing time required. A static-timing analysis technique according to the present invention comprises a net-list input step S110 which inputs per-transistor basis connection information, to construct an internal data structure for analysis; an expected-value check step S120 which checks, against the above-mentioned internal data structure, each node on whether its expected values may be a high-impedance state; a signal-flow direction narrow-down step S130 which narrows down the directions in which the transistor signal may flow, based on the obtained expected values; a division step S140 which divides a sequential circuit into units consisting of only combinational sub-circuits; a path search step S150 which searches paths for each of thus divided units; and an output step S170 which outputs the obtained results.

摘要翻译： 本发明提供了一种用于分析LSI的静态定时的系统和方法，其涉及输出结果中包含的少量虚路径，并且还减少了所需的处理时间。 根据本发明的静态时序分析技术包括输入每晶体管基连接信息的网络列表输入步骤S110，以构建用于分析的内部数据结构; 预测值检查步骤S120，其针对上述内部数据结构检查每个节点关于其预期值是否可能是高阻抗状态; 基于所获得的期望值，使晶体管信号可能流过的方向变窄的信号流动方向缩小步骤S130; 将顺序电路分为仅由组合子电路组成的单元的分割步骤S140; 路径搜索步骤S150，其针对每个这样划分的单元的路径进行搜索; 以及输出步骤S170，其输出所获得的结果。

公开(公告)号：US06223333B1

公开(公告)日：2001-04-24

申请号：US08882495

申请日：1997-06-25

申请人： Mototaka Kuribayashi ,  Hideki Takeuchi ,  Junichi Tsujimoto

发明人： Mototaka Kuribayashi ,  Hideki Takeuchi ,  Junichi Tsujimoto

IPC分类号： G06F1750

CPC分类号： G06F17/5031

摘要： In the timing analysis method, connection information is compared to circuit patterns that have been stored in a memory in advance after reading the connection information of an electrical circuit, a connection information supplement process to supplement vertically circuit connection information regarding the matched circuit pattern for the stored connection information is performed when the connection information is matched with one of the registered circuit patterns, and a timing analysis of the connection information that has been supplemented by the connection information supplement process is executed.

摘要翻译： 在定时分析方法中，连接信息在读取电路的连接信息之后，预先与存储在存储器中的电路图案进行比较，连接信息补充处理用于补充垂直电路关于匹配电路图案的连接信息 当连接信息与注册的电路图案中的一个匹配时执行存储的连接信息，并且执行已经由连接信息补充处理补充的连接信息的定时分析。