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    System and method for analyzing static timing
    1.
    发明授权
    System and method for analyzing static timing 失效
    用于分析静态时序的系统和方法

    公开(公告)号：US5966521A

    公开(公告)日：1999-10-12

    申请号：US853908

    申请日：1997-05-09

    申请人： Hideki Takeuchi ,  Mototaka Kuribayashi ,  Junichi Tsujimoto ,  Kentaro Kuroiwa ,  Yasuhiro Tonooka

    发明人： Hideki Takeuchi ,  Mototaka Kuribayashi ,  Junichi Tsujimoto ,  Kentaro Kuroiwa ,  Yasuhiro Tonooka

    IPC分类号： G01R31/28 ,  G06F17/50 ,  H01L21/82

    CPC分类号： G06F17/5031

    摘要： The present invention provide a system and a method for analyzing the static timing for LSIs which involves rather a small number of false paths contained in output results and also which reduces the processing time required. A static-timing analysis technique according to the present invention comprises a net-list input step S110 which inputs per-transistor basis connection information, to construct an internal data structure for analysis; an expected-value check step S120 which checks, against the above-mentioned internal data structure, each node on whether its expected values may be a high-impedance state; a signal-flow direction narrow-down step S130 which narrows down the directions in which the transistor signal may flow, based on the obtained expected values; a division step S140 which divides a sequential circuit into units consisting of only combinational sub-circuits; a path search step S150 which searches paths for each of thus divided units; and an output step S170 which outputs the obtained results.

    摘要翻译： 本发明提供了一种用于分析LSI的静态定时的系统和方法，其涉及输出结果中包含的少量虚路径，并且还减少了所需的处理时间。 根据本发明的静态时序分析技术包括输入每晶体管基连接信息的网络列表输入步骤S110，以构建用于分析的内部数据结构; 预测值检查步骤S120，其针对上述内部数据结构检查每个节点关于其预期值是否可能是高阻抗状态; 基于所获得的期望值，使晶体管信号可能流过的方向变窄的信号流动方向缩小步骤S130; 将顺序电路分为仅由组合子电路组成的单元的分割步骤S140; 路径搜索步骤S150，其针对每个这样划分的单元的路径进行搜索; 以及输出步骤S170，其输出所获得的结果。

    Pattern matching method, timing analysis method and timing analysis device
    2.
    发明授权
    Pattern matching method, timing analysis method and timing analysis device 失效
    模式匹配方法，时序分析方法和时序分析装置

    公开(公告)号：US06223333B1

    公开(公告)日：2001-04-24

    申请号：US08882495

    申请日：1997-06-25

    申请人： Mototaka Kuribayashi ,  Hideki Takeuchi ,  Junichi Tsujimoto

    发明人： Mototaka Kuribayashi ,  Hideki Takeuchi ,  Junichi Tsujimoto

    IPC分类号： G06F1750

    CPC分类号： G06F17/5031

    摘要： In the timing analysis method, connection information is compared to circuit patterns that have been stored in a memory in advance after reading the connection information of an electrical circuit, a connection information supplement process to supplement vertically circuit connection information regarding the matched circuit pattern for the stored connection information is performed when the connection information is matched with one of the registered circuit patterns, and a timing analysis of the connection information that has been supplemented by the connection information supplement process is executed.

    摘要翻译： 在定时分析方法中，连接信息在读取电路的连接信息之后，预先与存储在存储器中的电路图案进行比较，连接信息补充处理用于补充垂直电路关于匹配电路图案的连接信息 当连接信息与注册的电路图案中的一个匹配时执行存储的连接信息，并且执行已经由连接信息补充处理补充的连接信息的定时分析。

    Method of reducing circuit data, method of simulating circuit, and medium for storing circuit data reduction program
    3.
    发明授权
    Method of reducing circuit data, method of simulating circuit, and medium for storing circuit data reduction program 失效
    减少电路数据的方法，模拟电路的方法和用于存储电路数据简化程序的介质

    公开(公告)号：US06374205B1

    公开(公告)日：2002-04-16

    申请号：US09248989

    申请日：1999-02-12

    申请人： Mototaka Kuribayashi ,  Masaaki Yamada ,  Hideki Takeuchi

    发明人： Mototaka Kuribayashi ,  Masaaki Yamada ,  Hideki Takeuchi

    IPC分类号： G06F9455

    CPC分类号： G06F17/5036

    摘要： A method reduces circuit data to be simulated, by extracting element data that influences a result of simulation out of the circuit data, thereby shortening a simulation time while maintaining the accuracy of simulation. Also provided is a simulation method that employs the reduction method. The method includes the steps of entering one of an input vector and/or an observation point for the circuit data to be simulated, and extracting an element data corresponding to a node influenced by propagation of a varying state of the input signal, the varying state for the node having an influence for the observation point, from the circuit data according to the input vector and/or observation point. The extracted nodes and elements related thereto are used to prepare reduced circuit data that is simulated. The method reduces the scale of a circuit to simulate by extracting only essential elements that affect a result of simulation from circuit data such as a netlist that forms the circuit to be simulated.

    摘要翻译： 通过提取影响电路数据中的模拟结果的元素数据，减少模拟电路数据，从而缩短模拟时间，同时保持模拟精度。 还提供了采用还原方法的模拟方法。 该方法包括以下步骤：输入要被仿真的电路数据的输入矢量和/或观测点之一，以及提取与由输入信号的变化状态的传播影响的节点对应的元素数据，变化状态 对于具有对观察点的影响的节点，根据输入向量和/或观察点的电路数据，提取的节点和与其相关的元素用于准备被模拟的简化电路数据。 该方法通过从诸如形成要仿真的电路的网表等电路数据中提取仅影响仿真结果的基本元素来减小模拟电路的规模。

    DAMASCENE PROCESS FOR USE IN FABRICATING SEMICONDUCTOR STRUCTURES HAVING MICRO/NANO GAPS
    4.
    发明申请
    DAMASCENE PROCESS FOR USE IN FABRICATING SEMICONDUCTOR STRUCTURES HAVING MICRO/NANO GAPS 有权
    用于制造具有微米/纳米GAPS的半导体结构的大分子方法

    公开(公告)号：US20120171798A1

    公开(公告)日：2012-07-05

    申请号：US11737545

    申请日：2007-04-19

    申请人： Hideki Takeuchi ,  Emmanuel P. Quevy ,  Tsu-Jae King ,  Roger T. Howe

    发明人： Hideki Takeuchi ,  Emmanuel P. Quevy ,  Tsu-Jae King ,  Roger T. Howe

    IPC分类号： H01L21/02

    CPC分类号： B81C1/00142 ,  B81B2201/0271 ,  B81C2201/0109 ,  Y10S438/933

    摘要： In fabricating a microelectromechanical structure (MEMS), a method of forming a narrow gap in the MEMS includes a) depositing a layer of sacrificial material on the surface of a supporting substrate, b) photoresist masking and at least partially etching the sacrificial material to form at least one blade of sacrificial material, c) depositing a structural layer over the sacrificial layer, and d) removing the sacrificial layer including the blade of the sacrificial material with a narrow gap remaining in the structural layer where the blade of sacrificial material was removed.

    摘要翻译： 在制造微机电结构（MEMS）中，在MEMS中形成窄间隙的方法包括：a）在支撑衬底的表面上沉积牺牲材料层，b）光致抗蚀剂掩模并且至少部分蚀刻牺牲材料以形成 至少一个牺牲材料刀片，c）在所述牺牲层上沉积结构层，以及d）去除包括所述牺牲材料刀片的所述牺牲层，其中所述牺牲材料刀片被去除的所述结构层中残留有窄间隙 。

    Ultrasound diagnosis apparatus
    6.
    发明授权
    Ultrasound diagnosis apparatus 有权
    超声诊断仪

    公开(公告)号：US07217243B2

    公开(公告)日：2007-05-15

    申请号：US10869152

    申请日：2004-06-16

    申请人： Hideki Takeuchi

    发明人： Hideki Takeuchi

    IPC分类号： A61B8/00

    CPC分类号： G01S15/8925 ,  A61B8/483 ,  G01S7/52046 ,  G01S7/52079 ,  G01S7/5208 ,  G01S15/8927 ,  G10K11/346

    摘要： A plurality of 2D sub arrays are defined on a 2D array transducer for effecting transmission and reception of ultrasound. For each sub array, a plurality of groups are set. More specifically, a plurality of (16, for example) transducer elements forming a sub array are grouped or divided into a plurality of (4, for example) groups. A multiplexer sums a plurality of receiving signals output from the plurality of transducer elements for each group, and generates a group receiving signal. A plurality of group receiving signals thus generated are then subjected to a sub phase adjusting and summing process to form a sub phase adjusted and summed signal. A plurality of sub phase adjusted and summed signals corresponding to the plurality of sub arrays are then subjected to a main phase adjusting and summing process. A sub phase adjusting and summing processing section is provided within a probe head, a cable connector, or an apparatus body. During transmission, the multiplexer supplies a transmitting signal to a plurality of transducer elements forming a group in parallel.

    摘要翻译： 在2D阵列换能器上定义多个2D子阵列以实现超声波的发射和接收。 对于每个子阵列，设置多个组。 更具体地，形成子阵列的多个（16个例如）换能器元件被分组或分成多个（例如）4个组。 多路复用器对从每个组的多个换能器元件输出的多个接收信号相加，并产生组接收信号。 然后，如此生成的多个组接收信号经过子相位调整和求和处理，以形成子相位调整和求和信号。 然后，对应于多个子阵列的多个子相位调整和求和信号进行主相位调整和求和处理。 在探针头，电缆连接器或装置主体内设置有副相位调整和求和处理部。 在传输期间，多路复用器将发送信号提供给并联形成组的多个换能器元件。

    Semiconductor storage device including short circuit avoiding structure and method of fabricating thereof
    9.
    发明授权
    Semiconductor storage device including short circuit avoiding structure and method of fabricating thereof 失效
    包括短路避免结构的半导体存储装置及其制造方法

    公开(公告)号：US06255686B1

    公开(公告)日：2001-07-03

    申请号：US09124852

    申请日：1998-07-30

    申请人： Hideki Takeuchi ,  Hirohiko Izumi

    发明人： Hideki Takeuchi ,  Hirohiko Izumi

    IPC分类号： H01L27108

    CPC分类号： H01L27/10855 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76897 ,  H01L23/485 ,  H01L27/10885 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In a semiconductor storage device, an access transistor, which has a gate electrode and a pair of impurity diffusion layers, is formed at a device activation region defined by a device isolation structure of a semiconductor substrate. A first insulating film, which has a first contact hole for exposing a portion of the surface of one of the pair of impurity diffusion layers, is formed over the access transistor. A protective film, which has a second contact hole formed on the first contact hole, is formed on the first insulating film. A second insulating film is formed on the side wall faces of the first and second contact holes. A memory capacitor has a lower electrode and an upper part electrode which are opposed each other and are capacitive-coupled through a dielectric film. The lower electrode is filled inside the first and second contact holes to be formed in an island-like shape on the first insulating film through the protective film so as to be electrically connected with the one of the pair of impurity diffusion layers. Each of the first and second contact holes has a diameter which is made smaller by an existence of the second insulating film than a minimum dimension determined by an exposure limit in a photolithography.

    摘要翻译： 在半导体存储装置中，在由半导体衬底的器件隔离结构限定的器件激活区域处形成具有栅电极和一对杂质扩散层的存取晶体管。 在该存取晶体管的上方形成第一绝缘膜，该第一绝缘膜具有用于暴露该对杂质扩散层之一的表面的一部分的第一接触孔。 在第一绝缘膜上形成有形成在第一接触孔上的第二接触孔的保护膜。 第二绝缘膜形成在第一和第二接触孔的侧壁面上。 记忆电容器具有彼此相对并且通过电介质膜电容耦合的下部电极和上部电极。 下部电极填充在第一和第二接触孔的内部，以通过保护膜在第一绝缘膜上形成为岛状，以便与一对杂质扩散层电连接。 第一和第二接触孔中的每一个具有通过第二绝缘膜的存在使得比通过光刻中的曝光极限确定的最小尺寸更小的直径。

    Front part body structure of vehicle
    10.
    发明授权
    Front part body structure of vehicle 有权
    前部车身结构

    公开(公告)号：US08727428B2

    公开(公告)日：2014-05-20

    申请号：US13612110

    申请日：2012-09-12

    申请人： Hideki Takeuchi ,  Akihiro Matsui

    发明人： Hideki Takeuchi ,  Akihiro Matsui

    IPC分类号： B62D25/08

    CPC分类号： B62D25/082 ,  B62D25/088 ,  B62D25/14

    摘要： A front part body structure of a vehicle, includes: an upper frame which is extended in a longitudinal direction of the vehicle, one end of which is joined to a front pillar, and which includes an inner panel and an outer panel, the outer panel that is divided in a dividing part in the longitudinal direction of the vehicle; and a first partition wall which is provided between the inner panel and the outer panel, one end of which is joined to the inner panel, and the other end of which is fastened and fixed to the dividing part of the outer panel by means of a fastening member.

    摘要翻译： 车辆的前部车体结构包括：上框架，其在车辆的纵向方向上延伸，其一端接合到前柱，并且包括内板和外板，外板 其被分割成车辆的纵向方向上的分割部分; 以及第一分隔壁，其设置在所述内板和所述外板之间，其一端与所述内板接合，并且其另一端借助于所述外板紧固固定到所述外板的分割部 紧固件。