-
公开(公告)号：US08205801B2
公开(公告)日：2012-06-26
申请号：US12894719
申请日：2010-09-30
IPC分类号： G06K19/06
CPC分类号： G06K19/07 , G06K19/0701 , G11C5/142
摘要： A semiconductor device includes a memory portion, a logic portion, and a plurality of signal lines for electrically connecting the memory portion and the logic portion. In the case where a transfer rate between the semiconductor device and a communication device is α [bps], a first clock frequency generated in the logic portion is Kα [Hz] (K is an integer of 1 or more), the number of reading signal lines of the plurality of signal lines is n (n is an integer of 2 or more), and a second clock frequency generated in the logic portion is Lα/n [Hz] (L is any integer satisfying L/n
摘要翻译： 半导体器件包括用于电连接存储器部分和逻辑部分的存储器部分，逻辑部分和多条信号线。 在半导体器件和通信器件之间的传输速率为α[bps]的情况下，在逻辑部分中产生的第一时钟频率为Kα[Hz]（K为1以上的整数），读取次数 多条信号线的信号线为n（n为2以上的整数），在逻辑部分生成的第二时钟频率为Lα/ n [Hz]（L为满足L / n
-
公开(公告)号：US20110079650A1
公开(公告)日：2011-04-07
申请号：US12894719
申请日：2010-09-30
IPC分类号： G06K19/073 , G11C7/00
CPC分类号： G06K19/07 , G06K19/0701 , G11C5/142
摘要： A semiconductor device includes a memory portion, a logic portion, and a plurality of signal lines for electrically connecting the memory portion and the logic portion. In the case where a transfer rate between the semiconductor device and a communication device is α [bps], a first clock frequency generated in the logic portion is Kα [Hz] (K is an integer of 1 or more), the number of reading signal lines of the plurality of signal lines is n (n is an integer of 2 or more), and a second clock frequency generated in the logic portion is Lα/n [Hz] (L is any integer satisfying L/n
摘要翻译： 半导体器件包括用于电连接存储器部分和逻辑部分的存储器部分，逻辑部分和多条信号线。 在半导体器件和通信器件之间的传输速率为α[bps]的情况下，在逻辑部分中产生的第一时钟频率为Kα[Hz]（K为1以上的整数），读取次数 多条信号线的信号线为n（n为2以上的整数），在逻辑部分生成的第二时钟频率为Lα/ n [Hz]（L为满足L / n
-
公开(公告)号：US20090079572A1
公开(公告)日：2009-03-26
申请号：US11919497
申请日：2006-05-17
IPC分类号： G08B13/22
CPC分类号： G06K19/07749 , G06K19/0708
摘要： Initialization of a semiconductor device can be efficiently performed, which transmits and receives data through wireless communication. The semiconductor device includes an antenna, a power source circuit, a circuit which uses a DC voltage generated by the power source circuit as a power source voltage, and a resistor. The antenna includes a pair of terminals and receives a wireless signal (a modulated carrier wave). The power source circuit includes a first terminal and a second terminal and generates a DC voltage between the first terminal and the second terminal by using a received wireless signal (the modulated carrier wave). The resistor is connected between the first terminal and the second terminal. In this manner, the semiconductor device and the wireless communication system can transmit and receive data accurately.
摘要翻译： 可以有效地执行半导体器件的初始化，其通过无线通信发送和接收数据。 半导体器件包括天线，电源电路，使用由电源电路产生的直流电压作为电源电压的电路和电阻器。 天线包括一对终端，并接收无线信号（调制载波）。 电源电路包括第一端子和第二端子，并且通过使用接收的无线信号（调制载波）在第一端子和第二端子之间产生直流电压。 电阻器连接在第一端子和第二端子之间。 以这种方式，半导体器件和无线通信系统可以准确地发送和接收数据。
-
公开(公告)号：US08305216B2
公开(公告)日：2012-11-06
申请号：US13226770
申请日：2011-09-07
IPC分类号： G08B13/14
CPC分类号： G06K19/07749 , G06K19/0708
摘要： Initialization of a semiconductor device can be efficiently performed, which transmits and receives data through wireless communication. The semiconductor device includes an antenna, a power source circuit, a circuit which uses a DC voltage generated by the power source circuit as a power source voltage, and a resistor. The antenna includes a pair of terminals and receives a wireless signal (a modulated carrier wave). The power source circuit includes a first terminal and a second terminal and generates a DC voltage between the first terminal and the second terminal by using a received wireless signal (the modulated carrier wave). The resistor is connected between the first terminal and the second terminal. In this manner, the semiconductor device and the wireless communication system can transmit and receive data accurately.
摘要翻译： 可以有效地执行半导体器件的初始化，其通过无线通信发送和接收数据。 半导体器件包括天线，电源电路，使用由电源电路产生的直流电压作为电源电压的电路和电阻器。 天线包括一对终端，并接收无线信号（调制载波）。 电源电路包括第一端子和第二端子，并且通过使用接收的无线信号（调制载波）在第一端子和第二端子之间产生直流电压。 电阻器连接在第一端子和第二端子之间。 以这种方式，半导体器件和无线通信系统可以准确地发送和接收数据。
-
公开(公告)号：US07826552B2
公开(公告)日：2010-11-02
申请号：US11498808
申请日：2006-08-04
申请人： Hidetomo Kobayashi , Tomoaki Atsumi
发明人： Hidetomo Kobayashi , Tomoaki Atsumi
IPC分类号： H04L25/49
CPC分类号： H04L27/0008 , G06K19/0723 , H04B5/0056 , H04L27/04 , H04L27/12
摘要： The present invention provides a structure in which an amplitude-modulation mode and a frequency-modulation mode are switched. A semiconductor device of the invention has: a reset control circuit to which a modulation mode select signal which selects an amplitude-modulation mode or a frequency-modulation mode and Manchester-encoded information are input, which outputs a first reset signal and a second reset signal; a first frequency-dividing circuit to which a carrier wave is input, which outputs a sub-carrier wave responding to the amplitude-modulation mode or a frequency-modulation signal responding to the frequency-modulation mode, according to the first reset signal; a second frequency-dividing circuit which outputs a basic clock of which a duty ratio is different between the amplitude-modulation mode and the frequency-modulation mode, according to the second reset signal and an output of the first frequency-dividing circuit; and an ASK/FSK switching portion to which an output from the first frequency-dividing circuit and Manchester-encoded information are input, which outputs an amplitude-modulation signal or a frequency-modulation signal according to the modulation mode select signal.
摘要翻译： 本发明提供一种其中调制模式和调频模式被切换的结构。 本发明的半导体器件具有：复位控制电路，输入选择幅度调制模式或调频模式的调制模式选择信号和曼彻斯特编码信息，其输出第一复位信号和第二复位 信号; 输入载波的第一分频电路，根据第一复位信号输出响应于调幅模式的副载波或响应于调频模式的频率调制信号; 第二分频电路，根据第二复位信号和第一分频电路的输出，输出调幅方式和调幅方式之间的占空比不同的基本时钟; 以及输入来自第一分频电路和曼彻斯特编码信息的输出的ASK / FSK切换部分，其根据调制模式选择信号输出幅度调制信号或调频信号。
-
公开(公告)号：US20080153450A1
公开(公告)日：2008-06-26
申请号：US12003354
申请日：2007-12-21
申请人： Tomoaki Atsumi , Hidetomo Kobayashi
发明人： Tomoaki Atsumi , Hidetomo Kobayashi
IPC分类号： H04B1/16
CPC分类号： G06K19/0723 , G06K19/0702 , G06K19/07786 , H04B5/0062
摘要： A demodulation signal is generated by provision of a demodulation signal generation circuit to the semiconductor device capable of wireless communication and by obtainment of a difference between voltages having opposite polarities by the demodulation signal generation circuit. Alternatively, a plurality of demodulation signal generation circuits and a selective circuit which selects a demodulation signal generation circuit depending on characteristics of a received signal are provided, where operation of a second demodulation signal generation circuit stops when a first demodulation signal generation circuit is operated. The selective circuit includes an inverter circuit, a flip-flop circuit, and a selector circuit. When the second demodulation signal generation circuit has a comparator and the like, power consumption thereof is reduced.
摘要翻译： 通过向能够进行无线通信的半导体装置提供解调信号生成电路，并且通过解调信号生成电路获得具有相反极性的电压之间的差异来生成解调信号。 或者，提供多个解调信号生成电路和根据接收信号的特性来选择解调信号生成电路的选择电路，其中当第一解调信号产生电路被操作时第二解调信号产生电路的操作停止。 选择电路包括反相器电路，触发器电路和选择器电路。 当第二解调信号发生电路具有比较器等时，其功耗降低。
-
公开(公告)号：US08018341B2
公开(公告)日：2011-09-13
申请号：US11919497
申请日：2006-05-17
IPC分类号： G08B13/14
CPC分类号： G06K19/07749 , G06K19/0708
摘要： Initialization of a semiconductor device can be efficiently performed, which transmits and receives data through wireless communication. The semiconductor device includes an antenna, a power source circuit, a circuit which uses a DC voltage generated by the power source circuit as a power source voltage, and a resistor. The antenna includes a pair of terminals and receives a wireless signal (a modulated carrier wave). The power source circuit includes a first terminal and a second terminal and generates a DC voltage between the first terminal and the second terminal by using a received wireless signal (the modulated carrier wave). The resistor is connected between the first terminal and the second terminal. In this manner, the semiconductor device and the wireless communication system can transmit and receive data accurately.
摘要翻译： 可以有效地执行半导体器件的初始化，其通过无线通信发送和接收数据。 半导体器件包括天线，电源电路，使用由电源电路产生的直流电压作为电源电压的电路和电阻器。 天线包括一对终端，并接收无线信号（调制载波）。 电源电路包括第一端子和第二端子，并且通过使用接收的无线信号（调制载波）在第一端子和第二端子之间产生直流电压。 电阻器连接在第一端子和第二端子之间。 以这种方式，半导体器件和无线通信系统可以准确地发送和接收数据。
-
公开(公告)号：US07877068B2
公开(公告)日：2011-01-25
申请号：US12003354
申请日：2007-12-21
申请人： Tomoaki Atsumi , Hidetomo Kobayashi
发明人： Tomoaki Atsumi , Hidetomo Kobayashi
IPC分类号： H04B1/16
CPC分类号： G06K19/0723 , G06K19/0702 , G06K19/07786 , H04B5/0062
摘要： A demodulation signal is generated by provision of a demodulation signal generation circuit to the semiconductor device capable of wireless communication and by obtainment of a difference between voltages having opposite polarities by the demodulation signal generation circuit. Alternatively, a plurality of demodulation signal generation circuits and a selective circuit which selects a demodulation signal generation circuit depending on characteristics of a received signal are provided, where operation of a second demodulation signal generation circuit stops when a first demodulation signal generation circuit is operated. The selective circuit includes an inverter circuit, a flip-flop circuit, and a selector circuit. When the second demodulation signal generation circuit has a comparator and the like, power consumption thereof is reduced.
摘要翻译： 通过向能够进行无线通信的半导体装置提供解调信号生成电路，并且通过解调信号生成电路获得具有相反极性的电压之间的差异来生成解调信号。 或者，提供多个解调信号生成电路和根据接收信号的特性来选择解调信号生成电路的选择电路，其中当第一解调信号产生电路被操作时第二解调信号产生电路的操作停止。 选择电路包括反相器电路，触发器电路和选择器电路。 当第二解调信号发生电路具有比较器等时，其功耗降低。
-
公开(公告)号：US20070036237A1
公开(公告)日：2007-02-15
申请号：US11498808
申请日：2006-08-04
申请人： Hidetomo Kobayashi , Tomoaki Atsumi
发明人： Hidetomo Kobayashi , Tomoaki Atsumi
IPC分类号： H03C5/00
CPC分类号： H04L27/0008 , G06K19/0723 , H04B5/0056 , H04L27/04 , H04L27/12
摘要： The present invention provides a structure in which an amplitude-modulation mode and a frequency-modulation mode are switched. A semiconductor device of the invention has: a reset control circuit to which a modulation mode select signal which selects an amplitude-modulation mode or a frequency-modulation mode and Manchester-encoded information are input, which outputs a first reset signal and a second reset signal; a first frequency-dividing circuit to which a carrier wave is input, which outputs a sub-carrier wave responding to the amplitude-modulation mode or a frequency-modulation signal responding to the frequency-modulation mode, according to the first reset signal; a second frequency-dividing circuit which outputs a basic clock of which a duty ratio is different between the amplitude-modulation mode and the frequency-modulation mode, according to the second reset signal and an output of the first frequency-dividing circuit; and an ASK/FSK switching portion to which an output from the first frequency-dividing circuit and Manchester-encoded information are input, which outputs an amplitude-modulation signal or a frequency-modulation signal according to the modulation mode select signal.
摘要翻译： 本发明提供一种其中调制模式和调频模式被切换的结构。 本发明的半导体器件具有：复位控制电路，输入选择幅度调制模式或调频模式的调制模式选择信号和曼彻斯特编码信息，其输出第一复位信号和第二复位 信号; 输入载波的第一分频电路，根据第一复位信号输出响应于调幅模式的副载波或响应于调频模式的频率调制信号; 第二分频电路，根据第二复位信号和第一分频电路的输出，输出调幅方式和调幅方式之间的占空比不同的基本时钟; 以及输入来自第一分频电路和曼彻斯特编码信息的输出的ASK / FSK切换部分，其根据调制模式选择信号输出幅度调制信号或调频信号。
-
公开(公告)号：US07352604B2
公开(公告)日：2008-04-01
申请号：US11607053
申请日：2006-12-01
申请人： Yutaka Shionoiri , Tomoaki Atsumi , Kiyoshi Kato
发明人： Yutaka Shionoiri , Tomoaki Atsumi , Kiyoshi Kato
IPC分类号： G11C17/00
CPC分类号： G11C7/1096 , G11C7/1078 , G11C7/12 , G11C11/4094 , G11C17/12
摘要： According to the invention, mounting area is decreased and yield is improved by decreasing the number of elements, and a memory with less burden on peripheral circuitry and a driving method thereof are provided. The invention comprises a memory cell including a memory element in a region where a bit line and a word line cross with an insulator interposed between them, a column decoder, and a selector including a clocked inverter. An input node of the clocked inverter is connected to the bit line while an output node is connected to a data line. Among a plurality of transistors connected in series which form the clocked inverter, a gate of a P-type transistor of which source or drain is connected to a power source on the high potential side VDD and a gate of an N-type transistor of which source or drain is connected to a power source on the low potential side VSS are connected to the column decoder.
摘要翻译： 根据本发明，通过减少元件的数量来减小安装面积并提高产量，并且提供了对外围电路的负担较小的存储器及其驱动方法。 本发明包括一个存储单元，其中存储单元包括位线和字线与插在它们之间的绝缘体交叉的区域中的存储元件，列解码器和包括时钟反相器的选择器。 时钟反相器的输入节点连接到位线，而输出节点连接到数据线。 在形成时钟反相器的串联连接的多个晶体管中，源极或漏极连接到高电位侧VDD上的电源的P型晶体管的栅极和N型晶体管的栅极 源极或漏极连接到低电位侧的电源VSS连接到列解码器。
-
-
-
-
-
-
-
-
-
搜索结果
75 条记录 (耗时 0.031 秒)
