公开(公告)号：US07352604B2

公开(公告)日：2008-04-01

申请号：US11607053

申请日：2006-12-01

申请人： Yutaka Shionoiri ,  Tomoaki Atsumi ,  Kiyoshi Kato

发明人： Yutaka Shionoiri ,  Tomoaki Atsumi ,  Kiyoshi Kato

IPC分类号： G11C17/00

CPC分类号： G11C7/1096 ,  G11C7/1078 ,  G11C7/12 ,  G11C11/4094 ,  G11C17/12

摘要： According to the invention, mounting area is decreased and yield is improved by decreasing the number of elements, and a memory with less burden on peripheral circuitry and a driving method thereof are provided. The invention comprises a memory cell including a memory element in a region where a bit line and a word line cross with an insulator interposed between them, a column decoder, and a selector including a clocked inverter. An input node of the clocked inverter is connected to the bit line while an output node is connected to a data line. Among a plurality of transistors connected in series which form the clocked inverter, a gate of a P-type transistor of which source or drain is connected to a power source on the high potential side VDD and a gate of an N-type transistor of which source or drain is connected to a power source on the low potential side VSS are connected to the column decoder.

摘要翻译： 根据本发明，通过减少元件的数量来减小安装面积并提高产量，并且提供了对外围电路的负担较小的存储器及其驱动方法。 本发明包括一个存储单元，其中存储单元包括位线和字线与插在它们之间的绝缘体交叉的区域中的存储元件，列解码器和包括时钟反相器的选择器。 时钟反相器的输入节点连接到位线，而输出节点连接到数据线。 在形成时钟反相器的串联连接的多个晶体管中，源极或漏极连接到高电位侧VDD上的电源的P型晶体管的栅极和N型晶体管的栅极 源极或漏极连接到低电位侧的电源VSS连接到列解码器。

公开(公告)号：US07130234B2

公开(公告)日：2006-10-31

申请号：US10994259

申请日：2004-11-23

申请人： Yutaka Shionoiri ,  Tomoaki Atsumi ,  Kiyoshi Kato

发明人： Yutaka Shionoiri ,  Tomoaki Atsumi ,  Kiyoshi Kato

IPC分类号： G11C7/00

CPC分类号： G11C7/12 ,  G11C7/22

摘要： A semiconductor device includes a data holding unit, a precharge unit and a delay unit. The data holding unit includes a plurality of memory cells. The precharge unit includes a precharge potential line, a precharge signal line and a plurality of switches. The delay unit includes a plurality of transistors. In addition, the semiconductor device can further include one or both of an address selecting unit having a column-decoder and a row-decoder and a display unit having a plurality of pixels. Reading and writing of data can be accurately performed by preventing malfunction even with a delay in a selection of an address.

摘要翻译： 半导体器件包括数据保持单元，预充电单元和延迟单元。 数据保持单元包括多个存储单元。 预充电单元包括预充电电位线，预充电信号线和多个开关。 延迟单元包括多个晶体管。 此外，半导体器件还可以包括具有列解码器和行解码器的地址选择单元和具有多个像素的显示单元中的一个或两个。 即使延迟选择地址，也可以通过防止故障来准确地执行数据的读取和写入。

公开(公告)号：US20050140015A1

公开(公告)日：2005-06-30

申请号：US11005963

申请日：2004-12-07

申请人： Yutaka Shionoiri ,  Tomoaki Atsumi ,  Kiyoshi Kato

发明人： Yutaka Shionoiri ,  Tomoaki Atsumi ,  Kiyoshi Kato

IPC分类号： G03C1/85 ,  H01L23/48 ,  H01L27/12

CPC分类号： H01L27/12 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention has an object to provide a semiconductor device, an ID tag, in which delay of signal transmission with conductive layers is controlled. In addition, the other object is that a design method of such a semiconductor device is provided. A semiconductor device of the invention comprises a plurality of conductive layers, a plurality of first element groups each of which selects one among the conductive layers and a plurality of second element groups each of which amplifies a signal each transmitted from the conductive layers. Each of the second element groups is disposed between the first element groups. Stated another way, the first element group and the second element group are disposed alternately. The delay of the signal transmission with the plurality of conductive layers is controlled because a load by a parasitic capacitance is reduced due to the above feature.

摘要翻译： 本发明的目的是提供一种其中控制有导电层的信号​​传输延迟的半导体器件，ID标签。 此外，另一个目的是提供这种半导体器件的设计方法。 本发明的半导体器件包括多个导电层，多个第一元件组，每个第一元件组中的每一个选择导电层中的一个和多个第二元件组，每个第二元件组放大每个从导电层传输的信号。 每个第二元件组设置在第一元件组之间。 换句话说，第一元件组和第二元件组交替布置。 由于上述特征，由于寄生电容的负载减小，因此控制与多个导电层的信号​​传输的延迟。

公开(公告)号：US20050128827A1

公开(公告)日：2005-06-16

申请号：US10994259

申请日：2004-11-23

申请人： Yutaka Shionoiri ,  Tomoaki Atsumi ,  Kiyoshi Kato

发明人： Yutaka Shionoiri ,  Tomoaki Atsumi ,  Kiyoshi Kato

IPC分类号： G11C7/12 ,  G11C7/22 ,  G11C7/24 ,  G11C7/00

CPC分类号： G11C7/12 ,  G11C7/22

摘要： It is an object of the present invention to provide a semiconductor device in which reading and writing of data can be accurately performed by preventing malfunction even when a selection of address delays. A semiconductor device of the invention has three factors of a data holding unit, a precharge unit and a delay unit. The data holding unit comprises a plurality of memory cells. The precharge unit comprises a precharge potential line, a precharge signal line and a plurality of switches. The delay unit comprises a plurality of transistors. In addition, it has one or both of an address selecting unit having a column-decoder and a row-decoder and a display unit having a plurality of pixels, as well as the three factors.

摘要翻译： 本发明的目的是提供一种半导体器件，其中即使当选择地址延迟时，也可以通过防止故障来精确地执行数据的读取和写入。 本发明的半导体器件具有数据保持单元，预充电单元和延迟单元的三个因素。 数据保持单元包括多个存储单元。 预充电单元包括预充电电位线，预充电信号线和多个开关。 延迟单元包括多个晶体管。 此外，它具有地址选择单元，其具有列解码器和行解码器以及具有多个像素的显示单元以及三个因素中的一个或两个。

公开(公告)号：US07158439B2

公开(公告)日：2007-01-02

申请号：US10890173

申请日：2004-07-14

申请人： Yutaka Shionoiri ,  Tomoaki Atsumi ,  Kiyoshi Kato

发明人： Yutaka Shionoiri ,  Tomoaki Atsumi ,  Kiyoshi Kato

IPC分类号： G11C8/00

CPC分类号： G11C7/1096 ,  G11C7/1078 ,  G11C7/12 ,  G11C11/4094 ,  G11C17/12

摘要： A memory having a bit line, a word line crossing the bit line, a memory cell electrically connected to the bit line and to the word line, a column decoder and a selector including a clocked inverter having a plurality of transistors electrically connected in series between a first power source and a second power source is provided. An input node of the clocked inverter is connected to the bit line, an output node of the clocked inverter is electrically connected to a data line, the plurality of transistors comprise a P-type transistor and a N-type transistor, a gate electrode of the P-type transistor and a gate electrode of the N-type transistor are electrically connected to the column decoder, and a sense amplifier is not interposed between the bit line and the input node of the clocked inverter.

摘要翻译： 具有位线的存储器，与位线交叉的字线，电连接到位线和字线的存储单元，列解码器和选择器，包括时钟反相器，其具有串联电连接的多个晶体管 提供第一电源和第二电源。 时钟反相器的输入节点连接到位线，时钟反相器的输出节点电连接到数据线，多个晶体管包括P型晶体管和N型晶体管，栅极电极 P型晶体管和N型晶体管的栅极电连接到列解码器，并且读出放大器不插入在时钟反相器的位线和输入节点之间。

公开(公告)号：US07430146B2

公开(公告)日：2008-09-30

申请号：US11554128

申请日：2006-10-30

申请人： Yutaka Shionoiri ,  Tomoaki Atsumi ,  Kiyoshi Kato

发明人： Yutaka Shionoiri ,  Tomoaki Atsumi ,  Kiyoshi Kato

IPC分类号： G11C7/00

CPC分类号： G11C7/12 ,  G11C7/22

摘要： The semiconductor device in which reading and writing of data can be accurately performed by preventing malfunction even when a selection of address delays. The semiconductor device has three factors of a data holding unit, a precharge unit and a delay unit. The data holding unit includes a plurality of memory cells. The precharge unit includes a precharge potential line, a precharge signal line and a plurality of switches. The delay unit includes a plurality of transistors. In addition, it has one or both of an address selecting unit having a column-decoder and a row-decoder and a display unit having a plurality of pixels, as well as the three factors.

摘要翻译： 即使在选择地址延迟的情况下，也可以通过防止故障来准确地执行数据的读取和写入的半导体装置。 半导体器件具有数据保持单元，预充电单元和延迟单元的三个因素。 数据保持单元包括多个存储单元。 预充电单元包括预充电电位线，预充电信号线和多个开关。 延迟单元包括多个晶体管。 此外，它具有地址选择单元，其具有列解码器和行解码器以及具有多个像素的显示单元以及三个因素中的一个或两个。

公开(公告)号：US20070076515A1

公开(公告)日：2007-04-05

申请号：US11607053

申请日：2006-12-01

申请人： Yutaka Shionoiri ,  Tomoaki Atsumi ,  Kiyoshi Kato

发明人： Yutaka Shionoiri ,  Tomoaki Atsumi ,  Kiyoshi Kato

IPC分类号： G11C8/00

CPC分类号： G11C7/1096 ,  G11C7/1078 ,  G11C7/12 ,  G11C11/4094 ,  G11C17/12

摘要： According to the invention, mounting area is decreased and yield is improved by decreasing the number of elements, and a memory with less burden on peripheral circuitry and a driving method thereof are provided. The invention comprises a memory cell including a memory element in a region where a bit line and a word line cross with an insulator interposed between them, a column decoder, and a selector including a clocked inverter. An input node of the clocked inverter is connected to the bit line while an output node is connected to a data line. Among a plurality of transistors connected in series which form the clocked inverter, a gate of a P-type transistor of which source or drain is connected to a power source on the high potential side VDD and a gate of an N-type transistor of which source or drain is connected to a power source on the low potential side VSS are connected to the column decoder.

摘要翻译： 根据本发明，通过减少元件的数量来减小安装面积并提高产量，并且提供了对外围电路的负担较小的存储器及其驱动方法。 本发明包括一个存储单元，其中存储单元包括位线和字线与插在它们之间的绝缘体交叉的区域中的存储元件，列解码器和包括时钟反相器的选择器。 时钟反相器的输入节点连接到位线，而输出节点连接到数据线。 在形成时钟反相器的串联连接的多个晶体管中，源极或漏极连接到高电位侧VDD上的电源的P型晶体管的栅极和N型晶体管的栅极 源极或漏极连接到低电位侧的电源VSS连接到列解码器。

公开(公告)号：US20050047266A1

公开(公告)日：2005-03-03

申请号：US10890173

申请日：2004-07-14

申请人： Yutaka Shionoiri ,  Tomoaki Atsumi ,  Kiyoshi Kato

发明人： Yutaka Shionoiri ,  Tomoaki Atsumi ,  Kiyoshi Kato

IPC分类号： G11C17/18 ,  G11C7/10 ,  G11C7/12 ,  G11C8/00 ,  G11C11/4094 ,  G11C11/418 ,  G11C11/419 ,  G11C17/08 ,  G11C17/12 ,  H03K17/00 ,  H03K17/687 ,  H03K17/693

CPC分类号： G11C7/1096 ,  G11C7/1078 ,  G11C7/12 ,  G11C11/4094 ,  G11C17/12

摘要： According to the invention, mounting area is decreased and yield is improved by decreasing the number of elements, and a memory with less burden on peripheral circuitry and a driving method thereof are provided. The invention comprises a memory cell including a memory element in a region where a bit line and a word line cross with an insulator interposed between them, a column decoder, and a selector including a clocked inverter. An input node of the clocked inverter is connected to the bit line while an output node is connected to a data line. Among a plurality of transistors connected in series which form the clocked inverter, a gate of a P-type transistor of which source or drain is connected to a power source on the high potential side VDD and a gate of an N-type transistor of which source or drain is connected to a power source on the low potential side VSS are connected to the column decoder.

摘要翻译： 根据本发明，通过减少元件的数量来减小安装面积并提高产量，并且提供了对外围电路的负担较小的存储器及其驱动方法。 本发明包括一个存储单元，其中存储单元包括位线和字线与插在它们之间的绝缘体交叉的区域中的存储元件，列解码器和包括时钟反相器的选择器。 时钟反相器的输入节点连接到位线，而输出节点连接到数据线。 在形成时钟反相器的串联连接的多个晶体管中，源极或漏极连接到高电位侧VDD上的电源的P型晶体管的栅极和N型晶体管的栅极 源极或漏极连接到低电位侧的电源VSS连接到列解码器。

公开(公告)号：US07332815B2

公开(公告)日：2008-02-19

申请号：US11005963

申请日：2004-12-07

申请人： Yutaka Shionoiri ,  Tomoaki Atsumi ,  Kiyoshi Kato

发明人： Yutaka Shionoiri ,  Tomoaki Atsumi ,  Kiyoshi Kato

IPC分类号： G03C1/85

CPC分类号： H01L27/12 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention has an object to provide a semiconductor device, an ID tag, in which delay of signal transmission with conductive layers is controlled. In addition, the other object is that a design method of such a semiconductor device is provided.A semiconductor device of the invention comprises a plurality of conductive layers, a plurality of first element groups each of which selects one among the conductive layers and a plurality of second element groups each of which amplifies a signal each transmitted from the conductive layers. Each of the second element groups is disposed between the first element groups. Stated another way, the first element group and the second element group are disposed alternately. The delay of the signal transmission with the plurality of conductive layers is controlled because a load by a parasitic capacitance is reduced due to the above feature.

摘要翻译： 本发明的目的是提供一种其中控制有导电层的信号​​传输延迟的半导体器件，ID标签。 此外，另一个目的是提供这种半导体器件的设计方法。 本发明的半导体器件包括多个导电层，多个第一元件组，每个第一元件组中的每一个选择导电层中的一个，以及多个第二元件组，每个第二元件组放大每个从导电层传输的信号。 每个第二元件组设置在第一元件组之间。 换句话说，第一元件组和第二元件组交替布置。 由于上述特征，由于寄生电容的负载减小，因此控制与多个导电层的信号​​传输的延迟。

公开(公告)号：US20070064511A1

公开(公告)日：2007-03-22

申请号：US11554128

申请日：2006-10-30

申请人： Yutaka Shionoiri ,  Tomoaki Atsumi ,  Kiyoshi Kato

发明人： Yutaka Shionoiri ,  Tomoaki Atsumi ,  Kiyoshi Kato

IPC分类号： G11C7/00

CPC分类号： G11C7/12 ,  G11C7/22

摘要： It is an object of the present invention to provide a semiconductor device in which reading and writing of data can be accurately performed by preventing malfunction even when a selection of address delays. A semiconductor device of the invention has three factors of a data holding unit, a precharge unit and a delay unit. The data holding unit comprises a plurality of memory cells. The precharge unit comprises a precharge potential line, a precharge signal line and a plurality of switches. The delay unit comprises a plurality of transistors. In addition, it has one or both of an address selecting unit having a column-decoder and a row-decoder and a display unit having a plurality of pixels, as well as the three factors.

摘要翻译： 本发明的目的是提供一种半导体器件，其中即使当选择地址延迟时，也可以通过防止故障来精确地执行数据的读取和写入。 本发明的半导体器件具有数据保持单元，预充电单元和延迟单元的三个因素。 数据保持单元包括多个存储单元。 预充电单元包括预充电电位线，预充电信号线和多个开关。 延迟单元包括多个晶体管。 此外，它具有地址选择单元，其具有列解码器和行解码器以及具有多个像素的显示单元以及三个因素中的一个或两个。