-
1.发明授权公开(公告)号：US08159013B2
公开(公告)日：2012-04-17
申请号：US12524998
申请日：2009-02-24
IPC分类号： H01L29/66 , H01L29/94 , H01L21/108
CPC分类号： H01L27/0207 , H01L23/522 , H01L23/5286 , H01L27/11807 , H01L2924/0002 , H01L2924/00
摘要： There is provided a layout structure of a semiconductor integrated circuit capable of preventing the thinning of a metal wiring line close to a cell boundary and wire breakage therein without involving increases in the amount of data for OPC correction and OPC process time. In a region interposed between a power supply line and a ground line each placed to extend in a first direction, first and second cells each having a transistor and an intra-cell line each for implementing a circuit function are placed to be adjacent to each other in the first direction. In a boundary portion between the first and second cells, a metal wiring line extending in a second direction orthogonal to the first direction is placed so as not to short-circuit the power supply line and the ground line.
摘要翻译： 提供了一种半导体集成电路的布局结构，其能够防止金属布线在细胞边界附近的细化和线断裂，而不涉及用于OPC校正和OPC处理时间的数据量的增加。 在放置在第一方向上延伸的电源线和接地线之间的区域中，分别具有用于实现电路功能的晶体管和单元间线路的第一和第二单元彼此相邻 在第一个方向。 在第一和第二单元之间的边界部分中，放置沿与第一方向正交的第二方向延伸的金属布线，以便不使电源线和接地线短路。
-
公开(公告)号：US20100187699A1
公开(公告)日：2010-07-29
申请号：US12524998
申请日：2009-02-24
IPC分类号： H01L23/49
CPC分类号： H01L27/0207 , H01L23/522 , H01L23/5286 , H01L27/11807 , H01L2924/0002 , H01L2924/00
摘要： There is provided a layout structure of a semiconductor integrated circuit capable of preventing the thinning of a metal wiring line close to a cell boundary and wire breakage therein without involving increases in the amount of data for OPC correction and OPC process time. In a region interposed between a power supply line and a ground line each placed to extend in a first direction, first and second cells each having a transistor and an intra-cell line each for implementing a circuit function are placed to be adjacent to each other in the first direction. In a boundary portion between the first and second cells, a metal wiring line extending in a second direction orthogonal to the first direction is placed so as not to short-circuit the power supply line and the ground line.
摘要翻译： 提供了一种半导体集成电路的布局结构，其能够防止金属布线在细胞边界附近的细化和线断裂，而不涉及用于OPC校正和OPC处理时间的数据量的增加。 在放置在第一方向上延伸的电源线和接地线之间的区域中，分别具有用于实现电路功能的晶体管和单元间线路的第一和第二单元彼此相邻 在第一个方向。 在第一和第二单元之间的边界部分中，放置沿与第一方向正交的第二方向延伸的金属布线，以便不使电源线和接地线短路。
-
公开(公告)号：US20080169487A1
公开(公告)日：2008-07-17
申请号：US11968894
申请日：2008-01-03
IPC分类号： H01L27/10
CPC分类号： H01L27/0207
摘要： In a layout structure of a semiconductor integrated circuit, when transistors are arranged in a constant gate wiring pitch, a common source diffusion region is provided between two adjacent transistors, a CA via is provided on the common source diffusion region, and a source wiring connected to the CA via is provided on the common source diffusion region. An inter-drain wiring connecting the drain regions of the two transistors is formed in a wiring layer higher than the source wiring. Therefore, the wiring path of the source wiring is not limited by the wiring path of the inter-drain wiring, and can be provided, covering the common source diffusion region to a further extent. As a result, the number of high-resistance CA vias or the flexibility of arrangement is increased, leading to a reduction in source resistance, resulting in an increase in operating speed of the semiconductor integrated circuit.
摘要翻译： 在半导体集成电路的布局结构中，当晶体管以恒定栅极布线间距排列时，在两个相邻晶体管之间设置公共源极扩散区，在公共源极扩散区上设置有CA通孔，并且源极布线连接 到CA通孔设置在公共源极扩散区域上。 连接两个晶体管的漏极区域的漏极间布线形成在比源极布线高的布线层中。 因此，源极配线的布线路径不受限制于漏极间配线的布线路径，能够进一步覆盖公共源极扩散区域。 结果，高电阻CA通孔的数量或布置的灵活性增加，导致源极电阻的降低，导致半导体集成电路的工作速度的增加。
-
公开(公告)号：US08022549B2
公开(公告)日：2011-09-20
申请号：US12947344
申请日：2010-11-16
IPC分类号： H01L23/52
CPC分类号： H01L27/11807 , H01L27/0207
摘要： This invention prevents a break in a signal wire disposed between wire ends due to attenuation and improves production yields of devices. In a standard cell, a first signal wire extends in a first direction. Second and third signal wires extend in a second direction substantially perpendicular to the first direction and are facing each other across the first signal wire. The second and third signal wires have the widths larger than the width of the first signal wire.
摘要翻译： 本发明防止由于衰减引起的布线在线端之间的信号线断裂，并且提高了器件的产量。 在标准单元中，第一信号线在第一方向上延伸。 第二和第三信号线在基本上垂直于第一方向的第二方向上延伸并且跨越第一信号线彼此面对。 第二和第三信号线的宽度大于第一信号线的宽度。
-
公开(公告)号：US20080246160A1
公开(公告)日：2008-10-09
申请号：US12098035
申请日：2008-04-04
IPC分类号： H01L23/52
CPC分类号： H01L27/11807 , H01L27/0207
摘要： This invention prevents a break in a signal wire disposed between wire ends due to attenuation and improves production yields of devices. In a standard cell, a first signal wire extends in a first direction. Second and third signal wires extend in a second direction substantially perpendicular to the first direction and are facing each other across the first signal wire. The second and third signal wires have the widths larger than the width of the first signal wire.
摘要翻译： 本发明防止由于衰减引起的布线在线端之间的信号线断裂，并且提高了器件的产量。 在标准单元中，第一信号线在第一方向上延伸。 第二和第三信号线在基本上垂直于第一方向的第二方向上延伸并且跨越第一信号线彼此面对。 第二和第三信号线的宽度大于第一信号线的宽度。
-
公开(公告)号：US20110079914A1
公开(公告)日：2011-04-07
申请号：US12947344
申请日：2010-11-16
IPC分类号： H01L23/52
CPC分类号： H01L27/11807 , H01L27/0207
摘要： This invention prevents a break in a signal wire disposed between wire ends due to attenuation and improves production yields of devices. In a standard cell, a first signal wire extends in a first direction. Second and third signal wires extend in a second direction substantially perpendicular to the first direction and are facing each other across the first signal wire. The second and third signal wires have the widths larger than the width of the first signal wire.
摘要翻译： 本发明防止由于衰减引起的布线在线端之间的信号线断裂，并且提高了器件的产量。 在标准单元中，第一信号线在第一方向上延伸。 第二和第三信号线在基本上垂直于第一方向的第二方向上延伸并且跨越第一信号线彼此面对。 第二和第三信号线的宽度大于第一信号线的宽度。
-
公开(公告)号：US08143724B2
公开(公告)日：2012-03-27
申请号：US13211130
申请日：2011-08-16
IPC分类号： H01L23/52
CPC分类号： H01L27/11807 , H01L27/0207
摘要： This invention prevents a break in a signal wire disposed between wire ends due to attenuation and improves production yields of devices. In a standard cell, a first signal wire extends in a first direction. Second and third signal wires extend in a second direction substantially perpendicular to the first direction and are facing each other across the first signal wire. The second and third signal wires have the widths larger than the width of the first signal wire.
摘要翻译： 本发明防止由于衰减引起的布线在线端之间的信号线断裂，并且提高了器件的产量。 在标准单元中，第一信号线在第一方向上延伸。 第二和第三信号线在基本上垂直于第一方向的第二方向上延伸并且跨越第一信号线彼此面对。 第二和第三信号线的宽度大于第一信号线的宽度。
-
公开(公告)号：US20110298138A1
公开(公告)日：2011-12-08
申请号：US13211130
申请日：2011-08-16
IPC分类号： H01L23/52
CPC分类号： H01L27/11807 , H01L27/0207
摘要： This invention prevents a break in a signal wire disposed between wire ends due to attenuation and improves production yields of devices. In a standard cell, a first signal wire extends in a first direction. Second and third signal wires extend in a second direction substantially perpendicular to the first direction and are facing each other across the first signal wire. The second and third signal wires have the widths larger than the width of the first signal wire.
-
公开(公告)号：US07859023B2
公开(公告)日：2010-12-28
申请号：US12098035
申请日：2008-04-04
IPC分类号： H01L27/10
CPC分类号： H01L27/11807 , H01L27/0207
摘要： This invention prevents a break in a signal wire disposed between wire ends due to attenuation and improves production yields of devices. In a standard cell, a first signal wire extends in a first direction. Second and third signal wires extend in a second direction substantially perpendicular to the first direction and are facing each other across the first signal wire. The second and third signal wires have the widths larger than the width of the first signal wire.
摘要翻译： 本发明防止由于衰减引起的布线在线端之间的信号线断裂，并且提高了器件的产量。 在标准单元中，第一信号线在第一方向上延伸。 第二和第三信号线在基本上垂直于第一方向的第二方向上延伸并且跨越第一信号线彼此面对。 第二和第三信号线的宽度大于第一信号线的宽度。
-
公开(公告)号：US08648392B2
公开(公告)日：2014-02-11
申请号：US12947335
申请日：2010-11-16
申请人： Hidetoshi Nishimura , Masaki Tamaru
发明人： Hidetoshi Nishimura , Masaki Tamaru
IPC分类号： H01L27/118
CPC分类号： H01L27/0207 , H01L27/11807
摘要： A plurality of PMOS transistors are provided on a substrate along an X-axis direction such that a gate length direction of each of the PMOS transistors is parallel to the X-axis direction. A plurality of NMOS transistors are provided on the substrate along the X-axis direction such that a gate length direction of each of the NMOS transistors is parallel to the X-axis direction, and each of the plurality of NMOS transistors is opposed to a corresponding one of the PMOS transistors in the Y-axis direction. Gate lines respectively correspond to the PMOS transistors and the NMOS transistors, and are arranged parallel to each other and extend linearly along the Y-axis direction such that each of the gate lines passes through gate areas of the PMOS transistors and NMOS transistors which correspond to each of the gate lines.
摘要翻译： 在X轴方向的基板上设置多个PMOS晶体管，使得PMOS晶体管的栅极长度方向平行于X轴方向。 多个NMOS晶体管沿着X轴方向设置在基板上，使得每个NMOS晶体管的栅极长度方向平行于X轴方向，并且多个NMOS晶体管中的每一个与相应的 一个PMOS晶体管在Y轴方向上。 栅极线分别对应于PMOS晶体管和NMOS晶体管，并且彼此平行地布置并且沿着Y轴方向线性延伸，使得每个栅极线通过PMOS晶体管的栅极区域和对应于 每条门线。
-
-
-
-
-
-
-
-
-
搜索结果
39 条记录 (耗时 0.021 秒)
