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1.发明授权Cell, standard cell, standard cell library, a placement method using standard cell, and a semiconductor integrated circuit 有权细胞，标准细胞，标准细胞库，使用标准细胞的放置方法和半导体集成电路公开(公告)号：US07503026B2
公开(公告)日：2009-03-10
申请号：US11305191
申请日：2005-12-19
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , H01L27/11807
摘要： A cell according to the present invention comprises a plurality of terminals capable of transmitting an input signal or an output signal and serving as a minimum unit in designing a semiconductor integrated circuit, wherein the plurality of terminals is located on routing grids lined in a Y direction which is a direction vertical to a power-supply wiring of the cell used in automatic placement & routing and has a shape extended in an X direction which is a direction in parallel with the power-supply wiring, more specifically such a shape that, for example, a longer-side dimension of the terminal is equal to “a routing grid interval in the X direction+a wiring width. According to the constitution, a cell area is reduced, which advantageously leads to the reduction of a chip area.
摘要翻译： 根据本发明的单元包括能够传输输入信号或输出信号并在设计半导体集成电路中作为最小单位的多个端子，其中多个端子位于沿Y方向排列的布线栅格上 其是与用于自动布置和布线的电池的电源布线垂直的方向，并且具有在与电源布线并联的方向的X方向上延伸的形状，更具体地说， 例如，终端的长边尺寸等于“X方向上的路由网格间隔+布线宽度”，根据该结构，小区面积减小，有利于芯片面积的减少。
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公开(公告)号：US20130027083A1
公开(公告)日：2013-01-31
申请号：US13562144
申请日：2012-07-30
IPC分类号： H01L25/00
CPC分类号： H01L27/0207 , H01L27/11807 , H01L2027/11822
摘要： A semiconductor integrated circuit device includes cells A-1, B-1, and C-1 that have the same logic. Cell B-1 has cell width W2 larger than a cell width of cell A-1, but gate length L1 of a MOS transistor is equal to that of cell A-1. Cell C-1 has cell width W2 equal to a cell width of cell B-1, but has a MOS transistor having large gate length L2. A circuit delay of cell C-1 becomes large as compared with that of cells A-1 and B-1, but leak current becomes small. Therefore, by replacing cell A-1 adjacent to a space area with cell B-1, and by replacing cell B-1 in a path having room in timing with cell C-1, for example, leak current can be suppressed without increasing a chip area.
摘要翻译： 半导体集成电路器件包括具有相同逻辑的单元A-1，B-1和C-1。 单元B-1具有大于单元A-1的单元宽度的单元宽度W2，但是MOS晶体管的栅极长度L1等于单元A-1的单元宽度。 单元C-1具有等于单元B-1的单元宽度的单元宽度W2，但是具有栅极长度L2大的MOS晶体管。 与电池A-1和B-1相比，电池C-1的电路延迟变大，但泄漏电流变小。 因此，通过用小区B-1替换与空间区域相邻的小区A-1，并且例如通过用小区C-1定时的具有空间的路径替换小区B-1，可以抑制泄漏电流而不增加 芯片面积。
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3.发明授权Semiconductor integrated circuit, standard cell, standard cell library, semiconductor integrated circuit designing method, and semiconductor integrated circuit designing equipment 有权半导体集成电路，标准单元，标准单元库，半导体集成电路设计方法和半导体集成电路设计设备公开(公告)号：US08261225B2
公开(公告)日：2012-09-04
申请号：US12714819
申请日：2010-03-01
申请人： Tetsurou Toubou , Nana Okamoto , Junichi Yano
发明人： Tetsurou Toubou , Nana Okamoto , Junichi Yano
IPC分类号： G06F17/50
CPC分类号： H01L27/11807 , G06F17/5072 , H01L27/0207
摘要： A semiconductor integrated circuit includes a first transistor which is formed of a first gate extending in a first direction and a first diffusion region and which is capable of being active, a second transistor which is formed of a second gate extending in the first direction and a second diffusion region and which is arranged adjacent to the first transistor in a second direction intersected at a right angle with the first direction, and a third gate which extends in the first direction and which is arranged adjacent in the second direction to the first transistor on an opposite side to the second transistor. A space between the first gate and the second gate is larger than a space between the first gate and the third gate.
摘要翻译： 半导体集成电路包括：第一晶体管，其由沿第一方向延伸的第一栅极和第一扩散区域形成，并且能够有效;第二晶体管，由沿第一方向延伸的第二栅极和 第二扩散区，并且在与第一方向成直角相交的第二方向上与第一晶体管相邻布置;以及第三栅极，其在第一方向上延伸并且在第二方向上相对于第一晶体管设置在第一方向上 与第二晶体管相反。 第一栅极和第二栅极之间的空间大于第一栅极和第三栅极之间的空间。
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4.发明授权Semiconductor integrated circuit, standard cell, standard cell library, semiconductor integrated circuit designing method, and semiconductor integrated circuit designing equipment 有权半导体集成电路，标准单元，标准单元库，半导体集成电路设计方法和半导体集成电路设计设备公开(公告)号：US07685551B2
公开(公告)日：2010-03-23
申请号：US11476124
申请日：2006-06-28
申请人： Tetsurou Toubou , Nana Okamoto , Junichi Yano
发明人： Tetsurou Toubou , Nana Okamoto , Junichi Yano
IPC分类号： G06F17/50
CPC分类号： H01L27/11807 , G06F17/5072 , H01L27/0207
摘要： A semiconductor integrated circuit includes a first transistor which is formed of a first gate extending in a first direction and a first diffusion region and which is capable of being active, a second transistor which is formed of a second gate extending in the first direction and a second diffusion region and which is arranged adjacent to the first transistor in a second direction intersected at a right angle with the first direction, and a third gate which extends in the first direction and which is arranged adjacent in the second direction to the first transistor on an opposite side to the second transistor. A space between the first gate and the second gate is larger than a space between the first gate and the third gate.
摘要翻译： 半导体集成电路包括：第一晶体管，其由沿第一方向延伸的第一栅极和第一扩散区域形成，并且能够有效;第二晶体管，由沿第一方向延伸的第二栅极和 第二扩散区，并且在与第一方向成直角相交的第二方向上与第一晶体管相邻布置;以及第三栅极，其在第一方向上延伸并且在第二方向上相对于第一晶体管设置在第一方向上 与第二晶体管相反。 第一栅极和第二栅极之间的空间大于第一栅极和第三栅极之间的空间。
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5.发明授权公开(公告)号：US08159013B2
公开(公告)日：2012-04-17
申请号：US12524998
申请日：2009-02-24
IPC分类号： H01L29/66 , H01L29/94 , H01L21/108
CPC分类号： H01L27/0207 , H01L23/522 , H01L23/5286 , H01L27/11807 , H01L2924/0002 , H01L2924/00
摘要： There is provided a layout structure of a semiconductor integrated circuit capable of preventing the thinning of a metal wiring line close to a cell boundary and wire breakage therein without involving increases in the amount of data for OPC correction and OPC process time. In a region interposed between a power supply line and a ground line each placed to extend in a first direction, first and second cells each having a transistor and an intra-cell line each for implementing a circuit function are placed to be adjacent to each other in the first direction. In a boundary portion between the first and second cells, a metal wiring line extending in a second direction orthogonal to the first direction is placed so as not to short-circuit the power supply line and the ground line.
摘要翻译： 提供了一种半导体集成电路的布局结构，其能够防止金属布线在细胞边界附近的细化和线断裂，而不涉及用于OPC校正和OPC处理时间的数据量的增加。 在放置在第一方向上延伸的电源线和接地线之间的区域中，分别具有用于实现电路功能的晶体管和单元间线路的第一和第二单元彼此相邻 在第一个方向。 在第一和第二单元之间的边界部分中，放置沿与第一方向正交的第二方向延伸的金属布线，以便不使电源线和接地线短路。
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公开(公告)号：US07369618B2
公开(公告)日：2008-05-06
申请号：US11132206
申请日：2005-05-19
IPC分类号： H04B3/00
CPC分类号： H04L25/028 , H04L25/0292 , H04L25/03878
摘要： A signal is transmitted in synchronization with a clock signal that repeats H and L levels indicating a preparation period and a transmission period, respectively. A transmitting circuit includes a transmitting capacitor, an input switch for setting a voltage in accordance with an input digital signal in the transmitting capacitor at preparation period, and a transmitting switch for generating a small voltage change in the signal line at transmission period, the voltage change being in accordance with a voltage of the transmitting capacitor. A receiving circuit includes an inverter with a CMOS configuration, a receiving capacitor inserted between an input terminal and an output terminal of the inverter, an equalizing switch for short-circuiting the input terminal and the output terminal of the inverter so as to set the voltage of the signal line to a predetermined voltage at preparation period, and a latch for supplying an output digital signal by performing logic amplification of the voltage of the output terminal of the inverter for each transmission period, and for holding the output for each preparation period.
摘要翻译： 与重复分别表示准备期间和发送期间的H，L电平的时钟信号同步地发送信号。 发送电路包括发送电容器，用于在准备期间根据发送电容器中的输入数字信号设定电压的输入开关和用于在发送期间产生信号线中的小电压变化的发送开关， 根据发送电容器的电压进行变化。 接收电路包括具有CMOS配置的反相器，插入在反相器的输入端子和输出端子之间的接收电容器，用于使逆变器的输入端子和输出端子短路的均衡开关，以便设置电压 的信号线在预备期间达到预定电压，以及锁存器，用于通过在每个传输周期内执行对逆变器的输出端子的电压的逻辑放大来提供输出数字信号，并且用于保持每个准备周期的输出。
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公开(公告)号：US20050207504A1
公开(公告)日：2005-09-22
申请号：US11132206
申请日：2005-05-19
IPC分类号： H03K19/096 , H03K17/04 , H03K19/0175 , H04L25/02 , H04L25/03 , H04L25/00
CPC分类号： H04L25/028 , H04L25/0292 , H04L25/03878
摘要： A signal is transmitted in synchronization with a clock signal that repeats H and L levels indicating a preparation period and a transmission period, respectively. A transmitting circuit includes a transmitting capacitor, an input switch for setting a voltage in accordance with an input digital signal in the transmitting capacitor at preparation period, and a transmitting switch for generating a small voltage change in the signal line at transmission period, the voltage change being in accordance with a voltage of the transmitting capacitor. A receiving circuit includes an inverter with a CMOS configuration, a receiving capacitor inserted between an input terminal and an output terminal of the inverter, an equalizing switch for short-circuiting the input terminal and the output terminal of the inverter so as to set the voltage of the signal line to a predetermined voltage at preparation period, and a latch for supplying an output digital signal by performing logic amplification of the voltage of the output terminal of the inverter for each transmission period, and for holding the output for each preparation period.
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公开(公告)号：US20050149895A1
公开(公告)日：2005-07-07
申请号：US11016805
申请日：2004-12-21
申请人： Tetsurou Toubou
发明人： Tetsurou Toubou
CPC分类号： G06F17/5022
摘要： A delay library of high accuracy is efficiently generated within a short time period. To this end, a set-up time is calculated by static analysis with no consideration of a delay caused by a wire; the initial value of the search range for the next binary search cycle is set such that the set-up time is the median value of the search range (for example, the range of 0.5 ns is set); and correct set-up time α is obtained using binary search based on the initial value of the search range.
摘要翻译： 在短时间内有效地产生高精度的延迟库。 为此，通过静态分析计算出安装时间，不考虑电线引起的延迟; 设置下一个二进制搜索周期的搜索范围的初始值，使得设置时间是搜索范围的中值（例如，设置0.5ns的范围）; 并且使用基于搜索范围的初始值的二进制搜索获得正确的设置时间α。
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公开(公告)号：US08178905B2
公开(公告)日：2012-05-15
申请号：US11972890
申请日：2008-01-11
申请人： Tetsurou Toubou
发明人： Tetsurou Toubou
IPC分类号： H01L23/52 , H01L23/50 , H01L23/535 , H01L21/82
CPC分类号： H01L27/092 , H01L27/0207
摘要： In a layout structure capable of independent supply of a substrate or well potential from a power supply potential, further reduction in layout area is achieved. A reinforcing power supply cell is inserted in a cell line in which a plurality of cells are arranged in series. Each of the cells includes an impurity doped region for supplying a substrate or well potential NWVDD which is different from a positive power supply potential VDD to a p-type transistor arranging region. The reinforcing power supply cell includes a power supply impurity doped region to which an impurity doped region of an adjacent cell is electrically connected and a power supply wire provided in a wiring layer formed above the power supply impurity doped region and electrically connected to the power supply impurity doped region.
摘要翻译： 在能够独立地提供基板或从电源电位的阱电位的布局结构中，实现了布局面积的进一步减小。 将增强供电单元插入其中多个单元串联布置的单元线中。 每个单元包括用于提供衬底的杂质掺杂区域或不同于正电源电位VDD的p型晶体管布置区域的阱势垒NWVDD。 加强电源单元包括电源杂质掺杂区域，相邻单元的杂质掺杂区域电连接到该电源杂质掺杂区域，以及电源线，其设置在形成在电源杂质掺杂区域上方并与电源电连接的布线层中 杂质掺杂区域。
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10.发明申请Semiconductor integrated circuit, standard cell, standard cell library, semiconductor integrated circuit designing method, and semiconductor integrated circuit designing equipment 有权半导体集成电路，标准单元，标准单元库，半导体集成电路设计方法和半导体集成电路设计设备公开(公告)号：US20070004147A1
公开(公告)日：2007-01-04
申请号：US11476124
申请日：2006-06-28
申请人： Tetsurou Toubou , Nana Okamoto , Junichi Yano
发明人： Tetsurou Toubou , Nana Okamoto , Junichi Yano
IPC分类号： H01L27/10 , H01L21/336
CPC分类号： H01L27/11807 , G06F17/5072 , H01L27/0207
摘要： A semiconductor integrated circuit includes a first transistor which is formed of a first gate extending in a first direction and a first diffusion region and which is capable of being active, a second transistor which is formed of a second gate extending in the first direction and a second diffusion region and which is arranged adjacent to the first transistor in a second direction intersected at a right angle with the first direction, and a third gate which extends in the first direction and which is arranged adjacent in the second direction to the first transistor on an opposite side to the second transistor. A space between the first gate and the second gate is larger than a space between the first gate and the third gate.
摘要翻译： 半导体集成电路包括：第一晶体管，其由沿第一方向延伸的第一栅极和第一扩散区域形成，并且能够有效;第二晶体管，由沿第一方向延伸的第二栅极和 第二扩散区，并且在与第一方向成直角相交的第二方向上与第一晶体管相邻布置;以及第三栅极，其在第一方向上延伸并且在第二方向上相对于第一晶体管设置在第一方向上 与第二晶体管相反。 第一栅极和第二栅极之间的空间大于第一栅极和第三栅极之间的空间。
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